EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 242

IC STRATIX II GX 90K 1152-FBGA

EP2SGX90EF1152C4N

Manufacturer Part Number
EP2SGX90EF1152C4N
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX90EF1152C4N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
90960
# I/os (max)
558
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520448
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1767
EP2SGX90EF35C4NES

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX90EF1152C4N
Manufacturer:
ALTERA
Quantity:
648
Part Number:
EP2SGX90EF1152C4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX90EF1152C4N
Manufacturer:
ALTERA
0
Timing Model
4–72
Stratix II GX Device Handbook, Volume 1
t
t
t
t
t
t
t
t
t
t
t
t
t
M512RC
M512WERESU
M512WEREH
M512DATASU
M512DATAH
M512WADDRSU
M512WADDRH
M512RADDRSU
M512RADDRH
M512DATACO1
M512DATACO2
M512CLKL
M512CLKH
Table 4–59. M512 Block Internal Timing Microparameters (Part 1 of 2)
Symbol
Synchronous
read cycle time
Write or read
enable setup
time before clock
Write or read
enable hold time
after clock
Data setup time
before clock
Data hold time
after clock
Write address
setup time before
clock
Write address
hold time after
clock
Read address
setup time before
clock
Read address
hold time after
clock
Clock-to-output
delay when using
output registers
Clock-to-output
delay without
output registers
Minimum clock
low time
Minimum clock
high time
Parameter
2089
22
203
22
203
22
203
22
203
298
2102
1315
1315
Min
-3 Speed
Grade(2)
2318
478
2345
Max
-3 Speed Grade
2089
23
213
23
213
23
213
23
213
298
2102
1380
1380
Min
(3)
2433
501
2461
Max
-4 Speed Grade -5 Speed Grade
2089
24
226
24
226
24
226
24
226
298
2102
1468
1468
Min
2587
533
2616
Max
2089
29
272
29
272
29
272
29
272
298
2102
1762
1762
Min
Altera Corporation
3104
640
3141
Max
June 2009
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps

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