EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 245

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

Altera Corporation
June 2009
(1)
(2)
(3)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MEGABESU
MEGABEH
MEGADATAASU
MEGADATAAH
MEGAADDRASU
MEGAADDRAH
MEGADATABSU
MEGADATABH
MEGAADDRBSU
MEGAADDRBH
MEGADATACO1
MEGADATACO2
MEGACLKL
MEGACLKH
MEGACLR
Table 4–61. M-RAM Block Internal Timing Microparameters (Part 2 of 2)
Symbol
The M512 block f
This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to –3 speed grades for EP2SGX130 devices.
Byte enable setup time
before clock
Byte enable hold time
after clock
A port data setup time
before clock
A port data hold time
after clock
A port address setup
time before clock
A port address hold
time after clock
B port setup time
before clock
B port hold time after
clock
B port address setup
time before clock
B port address hold
time after clock
Clock-to-output delay
when using output
registers
Clock-to-output delay
without output
registers
Minimum clock low
time
Minimum clock high
time
Minimum clear pulse
width
Parameter
MAX
obtained using the Quartus II software does not necessarily equal to 1/TMEGARC.
1950
1250
1250
Min
-347
-347
243
589
243
589
480
144
39
50
50
Grade
-9
-3 Speed
(2)
2899
Max
715
1950
1312
1312
Min
-365
-365
255
618
255
618
480
151
-10
40
52
52
Grade
-3 Speed
(3)
3042
Max
749
Stratix II GX Device Handbook, Volume 1
1950
1395
1395
Min
-388
-388
271
657
271
657
480
160
-11
DC and Switching Characteristics
43
55
55
-4 Speed
Grade
Note (1)
Max
3235
797
1950
1675
1675
-465
Min
-465
325
789
325
789
480
192
-13
-5 Speed
52
67
67
Grade
3884
Max
957
Unit
4–75
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps