EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 158

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

IEEE Std. 1149.1 JTAG Boundary-Scan Support
3–2
Stratix II GX Device Handbook, Volume 1
Notes to
(1)
(2)
SAMPLE/PRELOAD
EXTEST
BYPASS
USERCODE
IDCODE
HIGHZ
CLAMP
ICR instructions
PULSE_NCONFIG
CONFIG_IO
SignalTap II
instructions
Table 3–1. Stratix II GX JTAG Instructions
JTAG Instruction
Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
For more information on using the CONFIG_IO instruction, refer to the
for Altera Devices
(1)
(1)
(1)
Table
(2)
3–1:
White Paper.
00 0000 0101
00 0000 1111
11 1111 1111
00 0000 0111
00 0000 0110
00 0000 1011
00 0000 1010
00 0000 0001
00 0000 1101
Instruction Code
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation and permits an initial
data pattern to be output at the device pins. Also used by the
SignalTap II embedded logic analyzer.
Allows the external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
Places the 1-bit bypass register between the
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation.
Selects the 32-bit
TDI
out of
Selects the
allowing the
Places the 1-bit bypass register between the
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation, while
tri-stating all of the I/O pins.
Places the 1-bit bypass register between the
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation while
holding the I/O pins to a state defined by the data in the boundary-
scan register.
Used when configuring a Stratix II GX device via the JTAG port with
a USB-Blaster™, MasterBlaster™, ByteBlasterMV™, or
ByteBlaster II download cable, or when using a .jam or .jbc via an
embedded processor or JRunner.
Emulates pulsing the
even though the physical pin is unaffected.
Allows configuration of I/O standards through the JTAG chain for
JTAG testing. Can be executed before, during, or after
configuration. Stops configuration if executed during configuration.
Once issued, the
reset the configuration device.
configuration register is loaded and the TAP controller state
machine transitions to the
Monitors internal device operation with the SignalTap II embedded
logic analyzer.
and
TDO
TDO
.
IDCODE
IDCODE
pins, allowing the
CONFIG_IO
USERCODE
register and places it between
nCONFIG
to be serially shifted out of
UPDATE_DR
Description
MorphIO: An I/O Reconfiguration Solution
register and places it between the
nSTATUS
instruction holds
USERCODE
pin low to trigger reconfiguration
state.
is held low until the IOE
to be serially shifted
TDI
TDI
TDI
Altera Corporation
nSTATUS
TDO
and
and
and
TDI
October 2007
.
TDO
TDO
TDO
and
low to
pins,
pins,
pins,
TDO
,