EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 179

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

Altera Corporation
June 2009
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) Time taken to lock TX PLL from
(11) The 1.2 V RX V
(12) For AC-coupled links, the on-chip biasing circuit is switched off before and during configuration. Make sure that input
Bandwidth at
6.375 Gbps
Bandwidth at
3.125 Gbps
Bandwidth at
2.5 Gbps
TX PLL lock
time from
gxb_
powerdown
deassertion
(9),
PLD-Transceiver Interface
Interface
speed
Digital Reset
Pulse Width
Table 4–6. Stratix II GX Transceiver Block AC Specification (Part 6 of 6)
Description
Symbol /
(10)
The device cannot tolerate prolonged operation at this absolute maximum. Refer to
The rate matcher supports only up to +/-300 ppm.
This parameter is measured by embedding the run length data in a PRBS sequence.
This feature is only available in PCI-Express (PIPE) mode.
Time taken to
This is how long GXB needs to stay in LTR mode after
asserted in manual mode. Refer to
Time taken to recover valid data from GXB after
results are based on PRBS31, for native data rates only. Refer to
Time taken to recover valid data from GXB after
results are based on PRBS31, for native data rates only. Refer to
Please refer to the Protocol Characterization documents for lock times specific to the protocols.
specifications are not violated during this period.
Table
4–6:
BW = Low
BW = Med
BW = High
BW = Low
BW = Med
BW = High
BW = Low
BW = Med
BW = High
rx_pll_locked
Conditions
ICM
setting is intended for DC-coupled LVDS links.
-3 Speed Commercial
Min
gxb_powerdown
25
-
-
-
-
-
-
-
-
-
-
goes high from
Figure
Speed Grade
Typ
4–1.
2
3
7
3
5
9
1
2
4
-
-
rx_locktodata
rx_freqlocked
Max
rx_analogreset
100
250
-
-
-
-
-
-
-
-
-
Minimum is 2 parallel clock cycles
deassertion.
rx_pll_locked
-4 Speed Commercial
and Industrial Speed
Min
25
-
-
-
-
-
-
-
-
-
-
Figure
Figure
Stratix II GX Device Handbook, Volume 1
Grade
signal is asserted in manual mode. Measurement
signal goes high in automatic mode. Measurement
Typ
4–1.
4–1.
3
5
9
1
2
4
-
-
-
-
-
deassertion. Refer to
DC and Switching Characteristics
is asserted and before
Max
100
250
--
-
-
-
-
-
-
-
-
Figure 4–5
-5 Speed Commercial
Min
25
-
-
-
-
-
-
-
-
-
-
Speed Grade
Figure
for more information.
rx_locktodata
Typ
3
5
9
1
2
4
-
-
-
-
-
4–1.
Max
100
200
-
-
-
-
-
-
-
-
-
4–9
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
us
is