EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 240

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

Timing Model
4–70
Stratix II GX Device Handbook, Volume 1
(1)
(2)
t
t
t
t
t
t
t
t
t
t
t
PIN2COMBOUT_R
PIN2COMBOUT_C
COMBIN2PIN_R
COMBIN2PIN_C
CLR
PRE
CLKL
CLKH
SU
H
CO
Table 4–57. IOE Internal Timing Microparameters (Part 2 of 2)
Table 4–58. DSP Block Internal Timing Microparameters (Part 1 of 2)
Symbol
Symbol
This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to –3 speed grades for EP2SGX130 devices.
Row input pin to IOE
combinational output
Column input pin to
IOE combinational
output
Row IOE data input to
combinational output
pin
Column IOE data input
to combinational output
pin
Minimum clear pulse
width
Minimum preset pulse
width
Minimum clock low
time
Minimum clock high
time
Input, pipeline, and
output register setup
time before clock
Input, pipeline, and
output register hold
time after clock
Input, pipeline, and
output register
clock-to-output
delay
Parameter
Parameter
Min
180
1101
Grade
-3 Speed
50
Min
410
428
991
200
200
600
600
0
Grade
-3 Speed
(1)
Max
Max
2026
1854
(1)
0
760
787
Min
189
52
1101
Grade
Min
-3 Speed
0
410
428
991
210
210
630
630
Grade
-3 Speed
(2)
Max
Max
2127
1946
(2)
0
798
825
Min
1101
200
Min
55
410
428
991
223
223
669
669
-4 Speed
0
-4 Speed
Grade
Grade
Max
2261
2069
Max
848
878
0
1101
Altera Corporation
Min
Min
241
410
428
991
268
268
804
804
67
-5 Speed
-5 Speed
0
Grade
Grade
1018
1054
2439
2246
Max
Max
June 2009
0
Unit
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps