EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 160

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

Configuration
3–4
Stratix II GX Device Handbook, Volume 1
(AS), passive serial (PS), passive parallel asynchronous (PPA), and JTAG
configuration schemes. The Stratix II GX device’s optimized interface
allows microprocessors to configure it serially or in parallel and
synchronously or asynchronously. The interface also enables
microprocessors to treat Stratix II GX devices as memory and configure
them by writing to a virtual memory location, making reconfiguration
easy.
In addition to the number of configuration methods supported,
Stratix II GX devices also offer the design security, decompression, and
remote system upgrade features. The design security feature, using
configuration bitstream encryption and advanced encryption standard
(AES) technology, provides a mechanism to protect designs. The
decompression feature allows Stratix II GX FPGAs to receive a
compressed configuration bitstream and decompress this data in real-
time, reducing storage requirements and configuration time. The remote
system upgrade feature allows real-time system upgrades from remote
locations of Stratix II GX designs. For more information, refer to the
“Configuration Schemes” on page
Operating Modes
The Stratix II GX architecture uses SRAM configuration elements that
require configuration data to be loaded each time the circuit powers up.
The process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
configuration, the device resets registers, enables I/O pins, and begins to
operate as a logic device. The I/O pins are tri-stated during power-up,
and before and during configuration. Together, the configuration and
initialization processes are called command mode. Normal device
operation is called user mode.
SRAM configuration elements allow you to reconfigure Stratix II GX
devices in-circuit by loading new configuration data into the device. With
real-time reconfiguration, the device is forced into command mode with
a device pin. The configuration process loads different configuration
data, re-initializes the device, and resumes user-mode operation. You can
perform in-field upgrades by distributing new configuration files either
within the system or remotely.
The PORSEL pin is a dedicated input used to select power-on reset (POR)
delay times of 12 ms or 100 ms during power up. When the PORSEL pin
is connected to ground, the POR time is 100 ms. When the PORSEL pin is
connected to V
CC
, the POR time is 12 ms.
3–6.
Altera Corporation
October 2007