EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 88

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

TriMatrix Memory
2–80
Stratix II GX Device Handbook, Volume 1
f
Table 2–20
with the address and control signal input connections to the row unit
interfaces (L0 to L5 and R0 to R5).
Refer to the
Devices
information on TriMatrix memory.
Unit Interface Block
Table 2–20. M-RAM Row Interface Unit Signals
chapter in volume 2 of the Stratix II GX Device Handbook for more
R0
R1
R2
R3
R4
R5
L0
L1
L2
L3
L4
L5
shows the input and output data signal connections along
TriMatrix Embedded Memory Blocks in Stratix II & Stratix II GX
datain_a[29..15]
datain_a[35..30]
datain_a[41..36]
datain_a[56..42]
datain_a[71..57]
datain_b[29..15]
datain_b[35..30]
datain_b[41..36]
datain_b[56..42]
datain_b[71..57]
datain_a[14..0]
byteena_a[1..0]
byteena_a[3..2]
addressa[15..5]
byteena_a[5..4]
byteena_a[7..6]
datain_b[14..0]
byteena_b[1..0]
byteena_b[3..2]
addressb[15..5]
byteena_b[5..4]
byteena_b[7..6]
addressa[4..0]
addressb[4..0]
Input Signals
addr_ena_a
addr_ena_b
clocken_a
clocken_b
clock_a
renwe_a
clock_b
renwe_b
aclr_a
aclr_b
dataout_a[23..12]
dataout_a[35..24]
dataout_a[47..36]
dataout_a[59..48]
dataout_a[71..60]
dataout_b[23..12]
dataout_b[35..24]
dataout_b[47..36]
dataout_b[59..48]
dataout_b[71..60]
dataout_a[11..0]
dataout_b[11..0]
Output Signals
Altera Corporation
October 2007