EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 137

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

Figure 2–87. Stratix II GX I/O Banks
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
October 2007
PLL8
PLL7
PLL1
PLL2
Figure 2–87
representation only.
Depending on the size of the device, different device members have different numbers of V
pin list and the Quartus II software for exact locations.
Banks 9 through 12 are enhanced PLL external clock output banks.
Horizontal I/O banks feature SERDES and DPA circuitry for high-speed differential I/O standards. See the
High-Speed Differential I/O Interfaces with DPA in Stratix II & Stratix II GX Devices
Device Handbook 2 for more information on differential I/O standards.
VREF0B3 VREF1B3 VREF2B3 VREF3B3 VREF4B3
VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF0B8
This I/O bank supports LVDS
and LVPECL standards for input clock operation.
Differential HSTL and differential
SSTL standards are supported
for both input and output operations. (3)
DQS ×8
This I/O bank supports LVDS
and LVPECL standards
for input clock operations. Differential HSTL
and differential SSTL standards
are supported for both input
and output operations. (3)
DQS ×8
Figure
DQS ×8
DQS ×8
2–87:
is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical
Bank 3
Bank 8
DQS ×8
DQS ×8
Each I/O bank has its own VCCIO pins. A single device can support
1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different
V
support the voltage-referenced standards (such as SSTL-2).
Each I/O bank can support multiple standards with the same V
input and output pins. Each bank can support one V
example, when V
3.3-V PCI for inputs and outputs.
I/O banks 7, 8, 10 and 12 support all single-ended I/O
standards for both input and output operations. All differential
I/O standards are supported for both input and output operations
at I/O banks 10 and 12.
I/O Banks 3, 4, 9, and 11 support all single-ended
I/O standards for both input and output operations.
All differential I/O standards are supported for both
input and output operations at I/O banks 9 and 11.
CCIO
DQS ×8
DQS ×8
I/O banks 1 & 2 support LVTTL, LVCMOS,
2.5 V, 1.8 V, 1.5 V, SSTL-2, SSTL-18 class I,
LVDS, pseudo-differential SSTL-2 and pseudo-differential
SSTL-18 class I standards for both input and output
operations. HSTL-18 class II, SSTL-18 class II,
pseudo-differential HSTL and pseudo-differential
SSTL-18 class II standards are only supported for
input operations. (4)
level independently. Each bank also has dedicated VREF pins to
Notes
Bank 11
Bank 12
PLL11
PLL12
(1),
CCIO
Bank 9
Bank 10
PLL5
PLL6
(2)
is 3.3 V, a bank can support LVTTL, LVCMOS, and
VREF0B4 VREF1B4 VREF2B4 VREF3B4 VREF4B4
VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREF0B7
DQS ×8
DQS ×8
This I/O bank supports LVDS
and LVPECL standards for input clock
operation. Differential HSTL and differential
SSTL standards are supported
for both input and output operations. (3)
DQS ×8
DQS ×8
This I/O bank supports LVDS
and LVPECL standards for input clock
operation. Differential HSTL and
differential SSTL standards are
supported for both input and output
operations. (3)
Stratix II GX Device Handbook, Volume 1
DQS ×8
DQS ×8
Bank 4
Bank 7
chapter in volume 2 of the Stratix II
DQS ×8
DQS ×8
Stratix II GX Architecture
DQS ×8
DQS ×8
REF
REF
voltage level. For
groups. Refer to the
Transmitter: Bank 13
Receiver: Bank 13
REFCLK: Bank 13
Transmitter: Bank 14
Receiver: Bank 14
REFCLK: Bank 14
Transmitter: Bank 15
Receiver: Bank 15
REFCLK: Bank 15
CCIO
2–129
for