EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 13

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

Figure 2–3. Clock Distribution for the Transmitters
Note to
(1)
Altera Corporation
October 2007
Reference Clocks
(refclks,
Global Clock (1) ,
Inter-Transceiver
Lines)
The global clock line must be driven by an input pin.
Figure
2–3:
Central Block
Transmitter Channel [3..2]
Transmitter Channel [1..0]
Transmitter PLL Block
The transmitter PLLs in each transceiver block clock the PMA and PCS
circuitry in the transmit path. The Quartus II software automatically
powers down the transmitter PLLs that are not used in the design.
Figure 2–4
The transmitter phase/frequency detector references the clock from one
of the following sources:
■
■
■
■
Two reference clocks, REFCLK0 and REFCLK1, are available per
transceiver block. The inter-transceiver block bus allows multiple
transceivers to use the same reference clocks. Each transceiver block has
one outgoing reference clock which connects to one inter-transceiver
block line. The incoming reference clock can be selected from five
inter-transceiver block lines IQ[4..0] or from the global clock line that
is driven by an input pin.
Reference clocks
Reference clock from the adjacent transceiver block
Inter-transceiver block clock lines
Global clock line driven by input pin
is a block diagram of the transmitter PLL.
Note (1)
Transmitter Local
Clock Divider Block
Transmitter Local
Clock Divider Block
Central Clock
Gen Block
Divider Block
Gen Block
TX Clock
TX Clock
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
Transmitter High-Speed &
Transmitter High-Speed &
Low-Speed Clocks
Low-Speed Clocks
2–5