EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 303

IC STRATIX II GX 90K 1152-FBGA

EP2SGX90EF1152C4N

Manufacturer Part Number
EP2SGX90EF1152C4N
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX90EF1152C4N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
90960
# I/os (max)
558
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520448
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1767
EP2SGX90EF35C4NES

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX90EF1152C4N
Manufacturer:
ALTERA
Quantity:
648
Part Number:
EP2SGX90EF1152C4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX90EF1152C4N
Manufacturer:
ALTERA
0
(1)
Number of DQS Delay Buffer Stages
Table 4–114. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (t
Delay stages used for request DQS phase shift are reported in a project’s Compilation Report in the Quartus II
software. For example, phase-shift error on two delay stages under -3 conditions is 50 ps peak-to-peak or 25 ps.
1
2
3
4
(1)
(2)
Number of DQS Delay Buffer Stages
Table 4–112. DLL Frequency Range Specifications (Part 2 of 2)
Table 4–113. DQS Jitter Specifications for DLL-Delayed Clock (t
Note (1)
Frequency Mode
Peak-to-peak period jitter on the phase-shifted DQS clock. For example, jitter on
two delay stages under commercial conditions is 200 ps peak-to-peak or 100 ps.
Delay stages used for requested DQS phase shift are reported in a project’s
Compilation Report in the Quartus II software.
(1)
3
–3 Speed Grade (ps) –4 Speed Grade (ps) –5 Speed Grade (ps)
(2)
1
2
3
4
100
25
50
75
240 to 350 (–4 and –5 speed grade)
240 to 400 (–3 speed grade)
Frequency Range (MHz)
Commercial (ps)
120
30
60
90
110
130
160
80
DQS
_
PSERR
)
Industrial (ps)
Resolution
(Degrees)
DQS
105
140
110
130
180
210
35
70
36
36
_
JITTER
)

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