EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 268

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

(1)
(2)
(3)
(4)
Differential
SSTL-18 Class I
LVDS
HyperTransport
Table 4–87. Stratix II GX I/O Output Delay for Row Pins (Part 4 of 4)
I/O Standard
This is the default setting in the Quartus II software.
The parameters are only available on the left side of the device.
This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to –3 speed grades for EP2SGX130 devices.
(2)
Strength
10 mA
Drive
4 mA
6 mA
8 mA
-
-
Maximum Input and Output Clock Toggle Rate
Maximum clock toggle rate is defined as the maximum frequency
achievable for a clock type signal at an I/O pin. The I/O pin can be a
regular I/O pin or a dedicated clock I/O pin.
The maximum clock toggle rate is different from the maximum data bit
rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz,
the maximum data bit rate for dual data rate (DDR) could be potentially
as high as 600 Mbps on the same I/O pin.
Tables 4–88
Tables 4–91
at 0 pF load.
toggle rate for a non 0 pF load.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
DIP
DIP
DIP
DIP
DIP
DIP
OP
OP
OP
OP
OP
OP
through
through
Commercial
Fast Corner
Table 4–97
Industrial/
1038
1042
1018
1021
1067
1024
1053
1010
995
999
975
978
4–96
4–90
specifies the derating factors for the output clock
specify the maximum output clock toggle rates
Grade
specify the maximum input clock toggle rates.
-3 Speed
1709
1654
1648
1593
1633
1578
1615
1560
1723
1668
1723
1668
(3)
Grade
-3 Speed
1793
1736
1729
1672
1713
1656
1694
1637
1808
1751
1808
1751
(4)
-4 Speed
Grade
1906
1846
1838
1778
1821
1761
1801
1741
1922
1862
1922
1862
-5 Speed
Grade
2046
1973
1975
1902
1958
1885
1937
1864
2089
2016
2089
2016
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps