EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 66

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

Adaptive Logic Modules
2–58
Stratix II GX Device Handbook, Volume 1
Carry Chain
The carry chain provides a fast carry function between the dedicated
adders in arithmetic or shared arithmetic mode. Carry chains can begin in
either the first ALM or the fifth ALM in a LAB. The final carry-out signal
is routed to an ALM, where it is fed to local, row, or column interconnects.
The Quartus II Compiler automatically creates carry chain logic during
compilation, or you can create it manually during design entry.
Parameterized functions, such as LPM functions, automatically take
advantage of carry chains for the appropriate functions. The Quartus II
Compiler creates carry chains longer than 16 (8 ALMs in arithmetic or
shared arithmetic mode) by linking LABs together automatically. For
enhanced fitting, a long carry chain runs vertically, allowing fast
horizontal connections to TriMatrix memory and DSP blocks. A carry
chain can continue as far as a full column. To avoid routing congestion in
one small area of the device when a high fan-in arithmetic function is
implemented, the LAB can support carry chains that only utilize either
the top half or the bottom half of the LAB before connecting to the next
LAB. The other half of the ALMs in the LAB is available for implementing
narrower fan-in functions in normal mode. Carry chains that use the top
four ALMs in the first LAB will carry into the top half of the ALMs in the
next LAB within the column. Carry chains that use the bottom four ALMs
in the first LAB will carry into the bottom half of the ALMs in the next
LAB within the column. Every other column of the LABs are top-half
bypassable, while the other LAB columns are bottom-half bypassable.
Refer to
carry chain interconnect.
Shared Arithmetic Mode
In shared arithmetic mode, the ALM can implement a three-input add. In
this mode, the ALM is configured with four 4-input LUTs. Each LUT
either computes the sum of three inputs or the carry of three inputs. The
output of the carry computation is fed to the next adder (either to adder1
in the same ALM or to adder0 of the next ALM in the LAB) using a
dedicated connection called the shared arithmetic chain. This shared
arithmetic chain can significantly improve the performance of an adder
tree by reducing the number of summation stages required to implement
an adder tree.
“MultiTrack Interconnect” on page 2–63
Figure 2–43
shows the ALM in shared arithmetic mode.
for more information on
Altera Corporation
October 2007