EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 62

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

Adaptive Logic Modules
2–54
Stratix II GX Device Handbook, Volume 1
using the bottom set of output drivers. The Quartus II Compiler
automatically selects the inputs to the LUT. Asynchronous load data for
the register comes from the datae or dataf input of the ALM. ALMs in
normal mode support register packing.
Figure 2–39. 6-Input Function in Normal Mode
Notes to
(1)
(2)
Extended LUT Mode
The extended LUT mode is used to implement a specific set of
seven-input functions. The set must be a 2-to-1 multiplexer fed by two
arbitrary five-input functions sharing four inputs.
template of supported seven-input functions utilizing extended LUT
mode. In this mode, if the seven-input function is unregistered, the
unused eighth input is available for register packing. Functions that fit
into the template shown in
functions often appear in designs as “if-else” statements in Verilog HDL
or VHDL code.
datae0
datae1
dataf0
dataf1
dataa
datab
datad
datac
(2)
If datae1 and dataf1 are used as inputs to the six-input function, datae0 and
dataf0 are available for register packing.
The dataf1 input is available for register packing only if the six-input function is
un-registered.
These inputs are available for register packing.
Figure
2–39:
6-Input
LUT
Figure 2–40
occur naturally in designs. These
D
D
Notes
reg0
reg1
Figure 2–40
Q
Q
(1),
Altera Corporation
(2)
October 2007
To general or
local routing
To general or
local routing
To general or
local routing
shows the