EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 251

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

Altera Corporation
June 2009
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Clock skew adder
EP2SGX30
Clock skew adder
EP2SGX60
Clock skew adder
EP2SGX90
C I N
C O U T
P L L C I N
P L L C O U T
C I N
C O U T
P L L C I N
P L L C O U T
Table 4–77. EP2SGX130 Column Pins Regional Clock Timing Parameters
Table 4–78. EP2SGX130 Row Pins Regional Clock Timing Parameters
Table 4–79. Clock Network Specifications (Part 1 of 2)
Parameter
Parameter
Name
(1)
(1)
(1)
Industrial
Industrial
-0.049
-0.149
-0.144
1.815
1.650
0.116
1.544
1.549
Fast Corner
Fast Corner
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Clock Network Skew Adders
The Quartus II software models skew within dedicated clock networks
such as global and regional clocks. Therefore, the intra-clock network
skew adder is not specified.
between any two clock networks driving any registers in the Stratix II GX
device.
Commercial
Commercial
-0.031
-0.132
-0.127
1.834
1.669
0.134
1.560
1.565
Description
-3 Speed
-3 Speed
Grade
Grade
3.218
3.218
0.349
0.361
3.195
3.195
0.342
0.34
Table 4–79
-4 Speed
-4 Speed
Stratix II GX Device Handbook, Volume 1
Grade
Grade
3.417
3.417
0.364
0.378
3.395
3.395
0.356
0.356
Min
specifies the intra-clock skew
DC and Switching Characteristics
Typ
-5 Speed
-5 Speed
Grade
Grade
4.087
4.087
0.426
0.444
4.060
4.060
0.417
0.417
Max
±100
±100
±110
±50
±50
±55
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ps
ps
ps
ps
ps
ps
4–81