EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 300

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

PLL Timing
Specifications
f
f
f
f
t
t
t
f
f
f
t
f
t
t
f
f
IN
INPFD
INDUTY
ENDUTY
INJITTER
OUTJITTER
FCOMP
OUT
OUTDUTY
SCANCLK
CONFIGEPLL
OUT_EXT
LOCK
DLOCK
SWITCHOVER
CLBW
Table 4–110. Enhanced PLL Specifications (Part 1 of 2)
Name
Input clock frequency
Input frequency to the PFD
Input clock duty cycle
External feedback input clock duty
cycle
Input or external feedback clock input
jitter tolerance in terms of period jitter.
Bandwidth
Input or external feedback clock input
jitter tolerance in terms of period jitter.
Bandwidth > 0.85 MHz
Dedicated clock output period jitter
External feedback compensation time
Output frequency for internal global or
regional clock
Duty cycle for external clock output
Scanclk frequency
Time required to reconfigure scan
chains for EPLLs
PLL external clock output frequency
Time required for the PLL to lock from
the time it is enabled or the end of
device configuration
Time required for the PLL to lock
dynamically after automatic clock
switchover between two identical clock
frequencies
Frequency range where the clock
switchover performs properly
PLL closed-loop bandwidth
Tables 4–110
operating in both the commercial junction temperature range (0 to 85 C)
and the industrial junction temperature range (–40 to 100 C), except for
the clock switchover and phase-shift stepping features. These two
features are only supported from the 0 to 100 C junction temperature
range.
≤
0.85 MHz
Description
and
4–111
describe the Stratix II GX PLL specifications when
1.5
1.5
0.13
Min
1.5
40
40
45
4
4
(2)
(2)
174/f
0.03
Typ
0.5
1.0
1.2
SCANCLK
50
1
100 MHz outclk
100 MHz outclk
25 mUI for <
250 ps for ≥
Max
16.9
500
420
550
100
500
60
60
10
55
(1)
1
1
ps or mUI
ns (peak-
ns (peak-
to-peak)
to-peak)
(p-p)
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
ms
ns
ns
%
%
%