EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 105

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

Altera Corporation
October 2007
The Stratix II GX clock networks can be disabled (powered down) by both
static and dynamic approaches. When a clock net is powered down, all
the logic fed by the clock net is in an off-state, thereby reducing the overall
power consumption of the device. The global and regional clock
networks can be powered down statically through a setting in the
configuration file (.sof or .pof). Clock networks that are not used are
automatically powered down through configuration bit settings in the
configuration file generated by the Quartus II software. The dynamic
clock enable and disable feature allows the internal logic to control power
up and down synchronously on GCLK and RCLK nets and PLL_OUT pins.
This function is independent of the PLL and is applied directly on the
clock network or PLL_OUT pin, as shown in
Enhanced and Fast PLLs
Stratix II GX devices provide robust clock management and synthesis
using up to four enhanced PLLs and four fast PLLs. These PLLs increase
performance and provide advanced clock interfacing and clock frequency
synthesis. With features such as clock switchover, spread spectrum
clocking, reconfigurable bandwidth, phase control, and reconfigurable
phase shifting, the Stratix II GX device’s enhanced PLLs provide you with
complete control of clocks and system timing. The fast PLLs provide
general purpose clocking with multiplication and phase shifting as well
as high-speed outputs for high-speed differential I/O support. Enhanced
and fast PLLs work together with the Stratix II GX high-speed I/O and
advanced clock architecture to provide significant improvements in
system performance and bandwidth.
Stratix II GX Device Handbook, Volume 1
Figures 2–67
Stratix II GX Architecture
through 2–69.
2–97