EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 40

IC STRATIX II GX 90K 1152-FBGA

EP2SGX90EF1152C4N

Manufacturer Part Number
EP2SGX90EF1152C4N
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX90EF1152C4N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
90960
# I/os (max)
558
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520448
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1767
EP2SGX90EF35C4NES

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX90EF1152C4N
Manufacturer:
ALTERA
Quantity:
648
Part Number:
EP2SGX90EF1152C4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX90EF1152C4N
Manufacturer:
ALTERA
0
Transceivers
Figure 2–25. Stratix II GX Block in Parallel Loopback Mode
2–32
Stratix II GX Device Handbook, Volume 1
FPGA
Logic
Array
Transmitter Digital Logic
Receiver Digital Logic
Incremental
Incremental
Generator
RX Phase
Compen-
Verify
BIST
BIST
sation
FIFO
Compensation
TX Phase
FIFO
Ordering
Serializer
Byte
Byte
Figure 2–25
Reverse Serial Loopback
The reverse serial loopback mode uses the analog portion of the
transceiver. An external source (pattern generator or transceiver)
generates the source data. The high-speed serial source data arrives at the
high-speed differential receiver input buffer, passes through the CRU
unit, and the retimed serial data is looped back and transmitted though
the high-speed differential transmitter output buffer.
20
serializer
Byte
De-
Encoder
8B/10B
shows the data path in parallel loopback mode.
BIST PRBS
Generator
Decoder
8B/10B
Match
Rate
FIFO
Deskew
FIFO
PRBS
BIST
Verify
Loopback
Parallel
Aligner
Word
Analog Receiver and
Transmitter Logic
Serializer
serializer
De-
Altera Corporation
Recovery
October 2007
Clock
Unit

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