EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 155

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

Altera Corporation
October 2007
Previous Chapter
02 changes:
June 2006, v1.2
Previous Chapter
02 changes:
April 2006, v1.1
Previous Chapter
02 changes:
October 2005
v1.0
Previous Chapter
03 changes:
August 2006, v1.4
Previous Chapter
03 changes:
June 2006, v1.3
Previous Chapter
03 changes:
April 2006, v1.2
Table 2–42. Document Revision History (Part 5 of 6)
Document
Date and
Version
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Added chapter to the Stratix II GX Device
Handbook.
●
●
●
●
●
●
●
●
●
●
●
Updated notes 1 and 2 in Figure 2–1.
Updated “Byte Serializer” section.
Updated Tables 2–4, 2–7, and 2–16.
Updated “Programmable Output Driver”
section.
Updated Figure 2–12.
Updated “Programmable Pre-Emphasis”
section.
Added Table 2–11.
Added “Dynamic Reconfiguration” section.
Added “Calibration Block” section.
Updated “Programmable Equalizer”
section, including addition of Figure 2–18.
Updated Figure 2–3.
Updated Figure 2–7.
Updated Table 2–4.
Updated “Transmit Buffer” section.
Updated Table 3–18 with note.
Updated note 2 in Figure 3–41.
Updated column title in Table 3–21.
Updated note 1 in Table 3–9.
Updated note 1 in Figure 3–40.
Updated note 2 in Figure 3–41.
Updated Table 3–16.
Updated Figure 3–56.
Updated Tables 3–19 through 3–22.
Updated Tables 3–25 and 3–26.
Updated “Fast PLL & Channel Layout”
section.
Changes Made
Stratix II GX Device Handbook, Volume 1
Updated input frequency range in
Table 2–4.
Updated input frequency range in
Table 2–4.
Added 1,152-pin FineLine BGA package
information for EP2SGX60 device in
Table 3–16.
Summary of Changes
Stratix II GX Architecture
2–147