EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 232

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

Timing Model
4–62
Stratix II GX Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
PCI
PCI-X
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL with OCT
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.5-V differential HSTL Class I
1.5-V differential HSTL Class II
1.8-V differential HSTL Class I
1.8-V differential HSTL Class II
LVDS
LVPECL
Table 4–53. Output Timing Measurement Methodology for Output Pins (Part 2 of 2)
(5)
Input measurement point at internal node is 0.5 V
Output measuring point for V
Input stimulus edge rate is 0 to V
Less than 50-mV ripple on V
V
CCPD
(5)
Table
I/O Standard
= 2.97 V, less than 50-mV ripple on V
4–53:
CCIO
MEAS
R
S
CC
and V
25
25
25
25
25
25
50
25
(
at buffer output is 0.5 V
Ω
in 0.2 ns (internal signal) from the driver preceding the I/O buffer.
)
CCPD
R
CCIO
, V
100
100
D
(
CCINT
Ω
and V
Loading and Termination
)
CCINT
= 1.15 V with less than 30-mV ripple.
CCPD
R
.
T
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
(
Ω
, V
CCIO
)
CCINT
.
V
CCIO
2.970
2.970
2.325
2.325
1.660
1.660
1.660
1.660
1.375
1.375
1.140
2.325
2.325
1.660
1.660
1.375
1.375
1.660
1.660
2.325
3.135
= 1.15 V.
(V)
V
1.123
1.123
0.790
0.790
0.790
0.790
0.648
0.648
1.123
1.123
0.790
0.790
0.648
0.648
0.790
0.790
TT
(V)
C
Notes
L
10
10
(pF)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Altera Corporation
(1), (2),
Measurement
V
1.1625
1.1625
0.6875
0.6875
1.1625
1.1625
0.6875
0.6875
1.1625
1.5675
MEAS
1.485
1.485
0.570
June 2009
Point
0.83
0.83
0.83
0.83
0.83
0.83
0.83
0.83
(3)
(V)