EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 304

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

JTAG Timing
Specifications
Figure 4–14
(1)
(1)
(2)
(3)
Table 4–115. DQS Bus Clock Skew Adder Specifications
(t
Table 4–116. DQS Phase Offset Delay Per Stage (ps)
DQS
This skew specification is the absolute maximum and minimum skew. For
example, skew on a 40 DQ group is 40 ps or 20 ps.
The delay settings are linear.
The valid settings for phase offset are -32 to +31.
The typical value equals the average of the minimum and maximum values.
Speed Grade
_CLOCK_SKEW_ADDER)
-3
-4
-5
18 DQ per DQS
36 DQ per DQS
4 DQ per DQS
9 DQ per DQS
shows the timing requirements for the JTAG signals
Mode
Min
Positive Offset
10
10
10
Max
15
15
16
DQS Clock Skew Adder (ps)
Min
Negative Offset
Notes
8
8
8
40
70
75
95
(1), (2),
Max
11
11
12
(1)
(3)