EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 145

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

Altera Corporation
October 2007
780-pin FineLine BGA
780-pin FineLine BGA
1,152-pin FineLine BGA
1,152-pin FineLine BGA
1,508-pin FineLine BGA
Table 2–38. EP2SGX30 Device Differential Channels
Table 2–39. EP2SGX60 Device Differential Channels
Table 2–40. EP2SGX90 Device Differential Channels
Package
Package
Package
Transmitter/Receiver
Transmitter/Receiver
Transmitter/Receiver Total Channels
Transmitter
16 transmitter channels in I/O bank 1 or a maximum of 29 transmitter
channels in I/O banks 1 and 2. The Quartus II software can also merge
receiver and transmitter PLLs when a receiver is driving a transmitter. In
this case, one fast PLL can drive both the maximum numbers of receiver
and transmitter channels.
Receiver
Transmitter
Transmitter
Transmitter
Transmitter
Receiver
Receiver
Receiver
Receiver
Total Channels
Channels
Total
45
47
59
59
29
31
29
31
42
42
Note (1)
Note (1)
Note (1)
PLL1
Center Fast PLLs
Stratix II GX Device Handbook, Volume 1
23
23
30
30
Center Fast PLLs
PLL1
16
17
21
21
Center Fast PLLs Package
PLL1
16
17
PLL2
22
24
29
29
PLL2
13
14
21
21
Stratix II GX Architecture
Corner Fast PLLs
PLL7
Corner Fast PLLs
23
23
29
29
PLL7
21
21
—
—
PLL2
13
14
PLL8
PLL8
22
24
29
29
2–137
21
21
—
—