EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 164

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

Configuration
3–8
Stratix II GX Device Handbook, Volume 1
f
memory, and transmit this compressed bitstream to Stratix II GX FPGAs.
During configuration, the Stratix II GX FPGA decompresses the bitstream
in real time and programs its SRAM cells. Stratix II GX FPGAs support
decompression in the FPP (when using a MAX II device or
microprocessor and flash memory), AS, and PS configuration schemes.
Decompression is not supported in the PPA configuration scheme nor in
JTAG-based configuration.
Remote System Upgrades
Shortened design cycles, evolving standards, and system deployments in
remote locations are difficult challenges faced by system designers.
Stratix II GX devices can help effectively deal with these challenges with
their inherent re programmability and dedicated circuitry to perform
remote system updates. Remote system updates help deliver feature
enhancements and bug fixes without costly recalls, reducing time to
market, and extending product life.
Stratix II GX FPGAs feature dedicated remote system upgrade circuitry to
facilitate remote system updates. Soft logic (Nios processor or user logic)
implemented in the Stratix II GX device can download a new
configuration image from a remote location, store it in configuration
memory, and direct the dedicated remote system upgrade circuitry to
initiate a reconfiguration cycle. The dedicated circuitry performs error
detection during and after the configuration process, recovers from any
error condition by reverting back to a safe configuration image, and
provides error status information. This dedicated remote system upgrade
circuitry avoids system downtime and is the critical component for
successful remote system upgrades.
Remote system configuration is supported in the following Stratix II GX
configuration schemes: FPP, AS, PS, and PPA. Remote system
configuration can also be implemented in conjunction with Stratix II GX
features such as real-time decompression of configuration data and
design security using AES for secure and efficient field upgrades.
Refer to the
chapter in volume 2 of the Stratix II GX Device Handbook for more
information about remote configuration in Stratix II GX devices.
Configuring Stratix II GX FPGAs with JRunner
The JRunner™ software driver configures Altera FPGAs, including
Stratix II GX FPGAs, through the ByteBlaster II or ByteBlasterMV cables
in JTAG mode. The programming input file supported is in Raw Binary
File (.rbf) format. JRunner also requires a Chain Description File (.cdf)
Remote System Upgrades with Stratix II & Stratix II GX Devices
Altera Corporation
October 2007