EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 42

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

Transceivers
Figure 2–27. Stratix II GX Block in Reverse Serial Pre-CDR Loopback Mode
Figure 2–28. Stratix II GX Block in PCI Express PIPE Reverse Parallel Loopback Mode
2–34
Stratix II GX Device Handbook, Volume 1
FPGA
Logic
Array
FPGA
Logic
Array
Transmitter Digital Logic
Receiver Digital Logic
Transmitter Digital Logic
Receiver Digital Logic
Incremental
Incremental
Generator
Incremental
Incremental
RX Phase
Generator
Compen-
RX Phase
Verify
Compen-
BIST
BIST
sation
FIFO
Verify
BIST
BIST
sation
FIFO
Compensation
Compensation
TX Phase
TX Phase
FIFO
FIFO
Ordering
Ordering
Serializer
Serializer
Byte
Byte
Byte
Byte
Figure 2–27
loopback mode.
PCI Express PIPE Reverse Parallel Loopback
This loopback mode, available only in PIPE mode, can be dynamically
enabled by the tx_detectrxloopback port of the PIPE interface.
Figure 2–28
20
20
serializer
serializer
Byte
De-
Byte
Encoder
De-
8B/10B
Encoder
8B/10B
PCI Express PIPE
show the Stratix II GX block in reverse serial pre-CDR
shows the datapath for this mode.
Reverse Parallel
Decoder
8B/10B
Decoder
Loopback
8B/10B
Generator
Generator
PRBS
BIST
PRBS
BIST
Match
FIFO
Rate
Match
Rate
FIFO
Deskew
Deskew
FIFO
FIFO
PRBS
Verify
BIST
PRBS
Verify
BIST
Aligner
Word
Aligner
Word
Analog Receiver and
Transmitter Logic
Analog Receiver and
Transmitter Logic
Serializer
serializer
Serializer
serializer
De-
De-
Altera Corporation
Reverse
Serial
Pre-CDR
Loopback
Recovery
Recovery
October 2007
Clock
Clock
Unit
Unit