EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 28

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

Transceivers
2–20
Stratix II GX Device Handbook, Volume 1
Figure 2–17. Deserializer
Note to
(1)
Word Aligner
The deserializer block creates 8-, 10-, 16-, or 20-bit parallel data. The
deserializer ignores protocol symbol boundaries when converting this
data. Therefore, the boundaries of the transferred words are arbitrary. The
word aligner aligns the incoming data based on specific byte or word
boundaries. The word alignment module is clocked by the local receiver
recovered clock during normal operation. All the data and programmed
patterns are defined as big-endian (most significant word followed by
least significant word). Most-significant-bit-first protocols such as
SONET/SDH should reverse the bit order of word align patterns
programmed.
This is a 10-bit deserializer. The deserializer can also convert 8, 16, or 20 bits of data.
parallel clock
High-speed
serial clock
Low-speed
Figure
2–17:
Note (1)
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D8
D9
Altera Corporation
October 2007
10