VT82C686B ETC-unknow, VT82C686B Datasheet
VT82C686B
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VT82C686B Summary of contents
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... Updated bit descriptions F2/3 Rx43 Updated bit descriptions F4 Rx41[1], 4D[3], 55[2], 57[0], D2[2] Updated bit descriptions ACPI I/O Rx5-4[8], Updated bit descriptions SMBus I/O Rx Updated bit descriptions F5 Rx Changed Audio / Game / MIDI ports to dedicated pins (SDD removed) Strap description removed from SPKR pin -i- VT82C686B Initials Revision History ...
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... Miscellaneous / General Purpose I/O.................................................................................................................................................... 62 Function 1 Registers - Enhanced IDE Controller .............................................................................................................. 68 PCI Configuration Space Header .......................................................................................................................................................... 68 IDE-Controller-Specific Confiiguration Registers ................................................................................................................................ 70 IDE I/O Registers.................................................................................................................................................................................. 74 Function 2 Registers - USB Controller Ports 0-1 ............................................................................................................... 75 PCI Configuration Space Header .......................................................................................................................................................... 75 USB-Specific Configuration Registers.................................................................................................................................................. 76 USB I/O Registers................................................................................................................................................................................. 77 Revision 1.71 June 9, 2000 T C ABLE OF ONTENTS .....................................................................................................................................I ..............................................................................................I -ii- VT82C686B Table of Contents ...
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... System and Processor Resume Events ................................................................................................................................................ 119 Legacy Power Management Timers .................................................................................................................................................... 120 System Primary and Secondary Events ............................................................................................................................................... 120 Peripheral Events ................................................................................................................................................................................ 120 ELECTRICAL SPECIFICATIONS............................................................................................................................................. 121 BSOLUTE AXIMUM ATINGS DC C .............................................................................................................................................................. 121 HARACTERISTICS PACKAGE MECHANICAL SPECIFICATIONS ...................................................................................................................... 122 Revision 1.71 June 9, 2000 ............................................................................................................................................... 121 -iii- VT82C686B Table of Contents ...
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... FIGURE 1. PC SYSTEM CONFIGURATION USING THE VT82C686B ................................................................................. 5 FIGURE 2. VT82C686B BALL DIAGRAM (TOP VIEW)........................................................................................................... 6 FIGURE 3. VT82C686B PIN LIST (NUMERICAL ORDER)...................................................................................................... 7 FIGURE 4. VT82C686B PIN LIST (ALPHABETICAL ORDER)............................................................................................... 8 FIGURE 5. STRAP OPTION CIRCUIT....................................................................................................................................... 60 FIGURE 6. POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM ......................................................................... 117 FIGURE 8. MECHANICAL SPECIFICATIONS – 352 PIN BALL GRID ARRAY PACKAGE......................................... 122 TABLE 1 ...
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... Serial interrupt for docking and non-docking applications Fast reset and Gate A20 operation Edge trigger or level sensitive interrupt Flash EPROM, 4Mb EPROM and combined BIOS support Supports positive and subtractive decoding Revision 1.71 June 9, 2000 VT82C686B PSIPC -I NTEGRATED ERIPHERAL PCI- OMPLIANT ...
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... Programmable control, status, monitor and alarm for flexible desktop management External thermister or internal bandgap temperature sensing Automatic clock throttling with integrated temperature sensing Internal core VCC voltage sensing Flexible external voltage sensing arrangement (any positive supply and battery) Revision 1.71 June 9, 2000 -2- VT82C686B Features ...
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... One additional steerable interrupt channel for on-board plug and play devices Microsoft Windows 98 Integrated I/O APIC (Advanced Peripheral Interrupt Controller) Built-in NAND-tree pin scan test capability 0.35um, 3.3V, low power CMOS process Single chip 27x27 mm, 352 pin BGA Revision 1.71 June 9, 2000 Windows NT , Windows 95 and plug and play BIOS compliant -3- VT82C686B Features ...
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... UltraDMA-100 (ATA-100) standards. The IDE controller is SFF-8038I v1.0 and Microsoft Windows-family compliant. b) Universal Serial Bus controller that is USB v1.1 and Universal HCI v1.1 compliant. The VT82C686B includes the root hub with four function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and isochronous peripherals to be inserted into the system with universal driver support ...
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... The VT82C686B also enhances the functionality of the standard ISA peripherals. The integrated interrupt controller supports both edge and level triggered interrupts channel by channel. The integrated DMA controller supports type F DMA in addition to standard ISA DMA modes. Compliant with the PCI-2.2 specification, the VT82C686B supports delayed transactions and remote power management so that slower ISA peripherals do not block the traffic of the PCI bus ...
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... Note: Some of the pins above have alternate functions and alternate names. The table above contains only one name (usually the most often used function), but the pin lists and pin descriptions contain all names. Revision 1.71 June 9, 2000 P INOUTS Figure 2. VT82C686B Ball Diagram (Top View ...
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... O DIR# H15 P VCC D09 O DRVDEN0 H16 IO AD15 D10 O TXD2 H17 IO AD14 D11 O DTR1# H18 IO AD13 Revision 1.71 June 9, 2000 Figure 3. VT82C686B Pin List (Numerical Order) Pin Pin Name H19 IO AD12 H20 IO AD11 J01 O RSTDRV J02 IO LA23 J03 IO LA22 J04 IO LA21 J05 IO LA20 ...
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... Figure 4. VT82C686B Pin List (Alphabetical Order) Pin Pin Name Pin Pin Name Y07 OD A20M# N04 I DRQ7 B13 I ACK# / DS1# D09 O DRVDEN0 W18 I ACBTCK D06 O DRVDEN1 U15 O ACRST B08 O DS0# V17 I ACSDI A08 O DS1# Y17 I ACSDI2 C06 I DSKCHG# Y16 O ACSDO C12 ...
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... Connect this pin to ground using a 100 Refer to the “PCI Mobile Design Guide” and the VIA “Apollo MVP4 Design Guide” for more details. PCI Reset. Active low reset signal for the PCI bus. The VT82C686B will assert this pin during power-up or from the control register. - input, DEVSEL# indicates the response to a resistor ...
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... OD Initialization. The VT82C686B asserts INIT if it detects a shut-down special cycle on the PCI bus soft reset is initiated by the register W7 OD Stop Clock. STPCLK# is asserted by the VT82C686B to the CPU to throttle the processor clock System Management Interrupt. SMI# is asserted by the VT82C686B to the CPU in response to different Power-Management events. ...
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... C Data. W10 I SMB Alert. (System Management Bus I/O space Rx08[ When the chip is enabled to allow it, assertion generates an IRQ or SMI interrupt or a power management resume event. The same pin is used as General Purpose Input 6 whose value is reflected in Rx48[6] of function 4 I/O space -11- VT82C686B 2 C Bus) Pinouts ...
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... I Primary Device DMA Request. Primary channel DMA request I Secondary Device DMA Request. Secondary channel DMA request O Primary Device DMA Acknowledge. Primary channel DMA acknowledge O Secondary Device DMA Acknowledge. Secondary channel DMA acknowledge I Primary Channel Interrupt. I Secondary Channel Interrupt. -12- VT82C686B Pinouts ...
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... Secondary Disk Address. SDA[2:0] are used to indicate which byte in either the ATA command block or control block is being accessed. IO Primary Disk Data IO Secondary Disk Data muxed with ISA Bus Address. O IDE Interrupt Request A. Output of internal block. O IDE Interrupt Request B. Output of internal block. -13- VT82C686B Pinouts ...
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... AC97 Interrupt Request. Output of internal block. O MC97 Interrupt Request. Output of internal block. Rx77[ Rx77[ Rx74[ Game Port Interface I/O Signal Description I Joystick A Button 1 I Joystick A Button 2 I Joystick B Button 1 I Joystick B Button 2 I Joystick A X-axis I Joystick A Y-axis I Joystick B X-axis I Joystick B Y-axis -14- VT82C686B Pinouts ...
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... Sense that the drive door is open or the diskette has been changed since the last drive selection. I Write Protect. Sense for detection that the diskette is write protected (causes write commands to be ignored) I FDC Interrupt Request. Rx75[ FDC DMA Request. Rx75[ -15- VT82C686B Pinouts ...
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... Error. Status output from the printer. Low indicates an error condition in the printer Busy. Status output from the printer. High indicates not ready to accept data Paper End. Status output from the printer. High indicates that it is out of paper Parallel Port Data -16- VT82C686B Pinouts ...
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... I Ring Indicator 2. Indicator to serial port 2 that external modem is detecting a ring condition. Used by software to initiate operations to answer and open the communications channel. Designed for direct input from external RS-232C receiver (whose input is typically not connected in direct connect environments). -17- VT82C686B Pinouts ...
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... Standard Memory Write. SMEMW# is the command to a memory slave, under 1MB, which indicates that it may latch data from the ISA data bus. O Bus Address Latch Enable. VT82C686B to indicate that the address (SA[19:0], LA[23:17] and the SBHE# signal) is valid I 16-Bit I/O Chip Select. This signal is driven by I/O devices on the ISA Bus to indicate that they support 16-bit I/O bus cycles ...
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... SDD is valid) when SA and SDD are multiplexed on SA pins 15-0 (i.e., when SPKR is strapped low to enable the audio interface pins). SOE# is tied directly to the output enable of 74F245 transceivers that buffer IDE Secondary Bus data and ISA-address (see SA pins for more information). -19- VT82C686B Pinouts ...
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... ISA-Bus data. The transceiver output enable may be grounded. SD0-7 connect to the “A” side of the transceiver and XD0-7 connect to the “B” side. XDIR high indicates that SD0-7 drives XD0-7. Serial IRQ I/O Signal Description I Serial IRQ (Rx68[ Rx74[ and Rx75[ Serial IRQ (Rx68[ and Rx74[ -20- VT82C686B Pinouts ...
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... Microcontroller Chip Select (Rx76[ Rx76[ Rx77[0] = 1). Asserted during read or write accesses to I/O ports 62h or 66h. O Microcontroller Chip Select (Alternate Pin) (Rx76[ selects MCCS# on pin U8, Rx76[ selects MCCS# on pin U5). Rx76[ enables MCCS# output on the selected pin. -21- VT82C686B Sampled at reset on SD[7-4] and latched into Pinouts ...
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... General Purpose Input 19 (Rx77[ General Purpose Input 20 (Rx77[ General Purpose Input 21 (Rx77[ W15 I General Purpose Input 22 (Rx77[ game disa) U14 I General Purpose Input 23 (Rx77[ game disa) n/a I General Purpose Inputs 16-23 (enabled RFSH# active) GPI if Rx77[ Rx77[ -22- VT82C686B Pinouts ...
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... General Purpose Output Write Enable (Rx74[ and Rx76[0] = 1). General Purpose I/Os Pin # I/O Signal Description T14 IO General Purpose I (Rx76[0] = 0). GPOWE# if Rx76[ See also Rx74[2] U12 IO General Purpose I See also Rx74[3] V14 IO General Purpose I 10. (Rx76[2] = 0). See also Rx74[ General Purpose I 11. (Rx76[3] = 0). See also Rx74[5] -23- VT82C686B Pinouts ...
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... Voltage Reference for Thermal Sensing (2.48V 5%) I Temperature Sense 1. I Temperature Sense 2. I Fan Speed Monitor 1. (3.3V only) I Fan Speed Monitor 2. I Chassis Intrusion Detect (Func 0 Rx76[2] = 1). Used for system security purposes. O Hardware Monitor Digital Test Out O Hardware Monitor Analog Test Out -24- VT82C686B Pinouts ...
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... N2 O Internal Thermal Alarm Output. (F4 Rx57[ Power Button. Used by the Power Management subsystem to monitor an external system on/off button or switch. The VT82C686B performs a 200us debounce of this input if Function 4 Rx40[5] is set to 1. (3.3V only Sleep Button. Used by the Power Management subsystem to monitor an I external system sleep button or switch ...
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... I Power Good. Connected to the PWRGOOD signal on the Power Supply. O PCI Reset. Active low reset signal for the PCI bus. The VT82C686B will assert this pin during power-up or from the control register. O Reset Drive. Reset signal to the ISA bus. Connect through an inverter to the chipset north bridge RESET# input and to PCI bus RESET# ...
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... Register Overview The following tables summarize the configuration and I/O registers of the VT82C686B. These tables also document the power-on default value (“Default”) and access type (“Acc”) for each register. Access type definitions used are RW (Read/Write), RO (Read/Only), “—” for reserved / used (essentially the same as RO), and RWC (or just WC) (Read / Write 1’ ...
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... Write Single Mask Default Acc RW D6 Write Mode RW D8 Clear Byte Pointer Master Clear DC Clear Mask Default Acc DE Read / Write Mask -28- VT82C686B Default Acc Default Acc RW Default Acc — * — * — RW — RW Default Acc RW ...
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... Baud Rate Generator Divisor A-F -undefined- Offset Serial Port 2 (Base = E8) 0 Transmit (Wr) / Receive (Rd) Buffer 1 Interrupt Enable 2 FIFO Control 2 Interrupt Status 3 UART Control 4 Handshake Control 5 UART Status 6 Handshake Status 7 Scratchpad 9-8 Baud Rate Generator Divisor A-F -undefined- -29- VT82C686B Default Acc -- ...
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... PnP IRQ/DRQ Test (do not program) Default Acc 88 PLL Test PLL Control PCS2/3 I/O Port Address Mask PCS Control 00 — 8D-8C PCS2# I/O Port Address 8F-8E PCS3# I/O Port Address 90-FF -reserved- -30- VT82C686B Default Acc — RW x4† — ...
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... Default Acc A Secondary Channel Status -reserved C-F Secondary Channel PRD Table Addr A8A8A8A8 — -31- VT82C686B Default Acc 07070707 — RW 0200 00 — RW 0200 00 — — — 00 — ...
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... USB Status 0000 RW 5-4 USB Interrupt Enable 0000 RW 7-6 Frame Number 00000000 RW B-8 Frame List Base Address Start Of Frame Modify 11-10 Port 2 Status / Control 0080 WC 0080 WC 13-12 Port 3 Status / Control 00 — 14-1F -reserved- -32- VT82C686B Default Acc RO 1106 3038 RO 0000 RW 0200 ...
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... — 0000 0000 — — — -33- VT82C686B Default Acc 0001 RW 00 — — Default Acc 0000 0001 RW 00 — — Register Overview ...
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... RW 0000 0000 WC 0000 0000 RW 0000 0000 RW 00 — Default Acc — — input — input RO 03FF FFFF RW 00 — -34- VT82C686B Default Acc 0000 RW 0000 RO 00 — Register Overview ...
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... — 00 — 00 — 00 — -35- VT82C686B Default Acc — — — — Register Overview ...
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... NMI Control 00 — 49 -reserved- 0000 RW 4B-4A Game Port Base Address 00 — 4C-FF -reserved- Note that these registers are the same as function 5 except for offset 44 (Read Only in function 5) -36- VT82C686B Default Acc RO 1106 3068 RO 0000 RW 0200 ...
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... Default Acc 0000 0000 RW 0000 0000 RO 00 — Default Acc — Default Acc 0330 RW 0200 RW -37- VT82C686B Default Acc — 0000 0000 WR RD 0000 0000 RO 0000 0000 — 0000 0000 WR ...
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... Processor” functions of the SoundBlaster Pro. Revision 1.71 June 9, 2000 I/O Registers – Game Port Default Acc Offset Game Port (200-20F typical -reserved Game Port Status RW 1 Start One-Shot WO 2-F -reserved -38- VT82C686B Default Acc Register Overview ...
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... Power-On Password Bytes Inaccessable ..default=0 Reserved ........................................always reads 0 A20 Address Line Enable 0 A20 disable / forced 0 (real mode) ........ default 1 A20 address line enable High Speed Reset 0 Normal 1 Briefly pulse system reset to switch from protected mode to real mode Register Descriptions - Legacy I/O Ports VT82C686B ...
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... This bit may be read back as status register bit-2 – – 1 Mouse Interrupt Enable 0 Keyboard Interrupt Enable -40- VT82C686B 0 No parity error (odd parity received)..... default 1 Even parity occurred on last byte received from keyboard / mouse 0 No error ................................................. default 1 Error 0 Mouse output buffer empty.................... default ...
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... Port 64 - Keyboard / Mouse Command .......................... WO This port is used to send commands to the keyboard / mouse controller. The command codes recognized by the VT82C686B are listed n the table below. Note: The VT82C686B Keyboard Controller is compatible with the VIA VT82C42 Industry-Standard Controller except that due to its integrated nature, many of the ...
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... Read Channel 4-7 Request Register ........... RO rd Port D0 –3 Read Channel 4 Mode Register .................. RO th Port D0 –4 Read Channel 5 Mode Register .................. RO th Port D0 –5 Read Channel 6 Mode Register .................. RO th Port D0 –6 Read Channel 7 Mode Register .................. RO Port DE –Channel 4-7 Read All Mask ............................. RO -42- Register Descriptions - Legacy I/O Ports VT82C686B ...
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... Port 40 – Counter 0 Base Count Value (LSB 1 Port 41 – Counter 1 Base Count Value (LSB 1 Port 42 – Counter 2 Base Count Value (LSB 1 -43- Register Descriptions - Legacy I/O Ports VT82C686B the shadow registers are ...
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... Update Ended Flag 3-0 0 Unused (always read 0) 7 VRT Reads 1 if VBAT voltage is OK 6-0 0 Unused (always read 0) Binary Range BCD Range 01-1Fh 01-0Ch 13-14h Register Descriptions - Legacy I/O Ports VT82C686B 00-59h 00-59h 00-59h 00-59h 01-12h 81-92h 00-23h 01-12h 81-92h 00-23h 01-07h 01-31h 01-12h 00-99h ...
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... Index E7 – Serial Port 1 I/O Base Address (00h) ........... RW I/O Address 9-3.........................................default = 0 7-1 0 Must be 0 ..............................................default = 0 Index E8 – Serial Port 2 I/O Base Address (00h) ........... RW 7-1 I/O Address 9-3.........................................default = 0 0 Must be 0 ..............................................default = 0 -45- Register Descriptions - Super-I/O I/O Ports VT82C686B ...
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... IRTX / IRRX Output from Serial Port 2...... def 1 Function 0 Rx76[ IRRX output from dedicated pin D12 IRTX output from dedicated pin E12 1-0 Reserved ........................................always reads 0 Index F2 – Test Mode (Do Not Program) ....................... RW Index F4 – Test Mode (Do Not Program) ....................... RW -46- Register Descriptions - Super-I/O I/O Ports VT82C686B ...
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... Floppy Drive 3 (see table below) 5-4 Floppy Drive 2 (see table below) 3-2 Floppy Drive 1 (see table below) 1-0 Floppy Drive 0 (see table below) DRVEN1 00 DRATE0 01 DRATE0 10 DRATE0 n/a 11 DRATE1 n/a n/a n -47- Register Descriptions - Super-I/O I/O Ports VT82C686B DRVEN0 DENSEL DRATE1 DENSEL# DRATE0 ...
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... E3h of the Super-I/O configuration registers). FDCBase is typically set to allow these ports to be accessed at the standard floppy disk controller address range of 3F0-3F7h. Port FDCBase+2 – FDC Command ................................. RW 7 Motor 3 (unused in VT82C686B: no MTR3# pin) 6 Motor 2 (unused in VT82C686B: no MTR2# pin) 5 Motor 1 0 ...
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... Interrupt pending (DMA & interrupts disabled) This bit is set hardware and must be written re-enable interrupts 1 FIFO Full ......................................................... RO 0 FIFO has at least 1 free byte 1 FIFO full or cannot accept byte 0 FIFO Empty......................................................... RO 0 FIFO contains at least 1 byte of data 1 FIFO is completely empty -49- Register Descriptions - Super-I/O I/O Ports VT82C686B ...
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... DSR Status (1=Active, 0=Inactive) 4 CTS Status (1=Active, 0=Inactive) 3 DCD Changed (1=Changed Since Last Read Changed (1=Changed Since Last Read) 1 DSR Changed (1=Changed Since Last Read) 0 CTS Changed (1=Changed Since Last Read) Port COM1Base+7 – Scratchpad .................................... RW 7 Scratchpad Data -50- Register Descriptions - Super-I/O I/O Ports VT82C686B ...
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... DSR Status (1=Active, 0=Inactive) 4 CTS Status (1=Active, 0=Inactive) 3 DCD Changed (1=Changed Since Last Read Changed (1=Changed Since Last Read) 1 DSR Changed (1=Changed Since Last Read) 0 CTS Changed (1=Changed Since Last Read) Port COM2Base+7 – Scratchpad .................................... RW 7 Scratchpad Data -51- Register Descriptions - Super-I/O I/O Ports VT82C686B ...
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... Finp = Input Filter Fout = Output Filter TFIL = Input Filter Type ST = Stereo / Mono Mode Select = Input Choices (0=Microphone, 1=CD, 3=Line) Command Summary – Sound Processor (see next page) -52- Register Descriptions - Super-I/O I/O Ports VT82C686B Test SSSC SSFC Multi Total Level (TL) Decay Rate (DR) Release Rate (RR) Block ...
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... Joystick B Button 1 Status 5 Joystick A Button 2 Status 4 Joystick A Button 1 Status 3 Joystick B One-Shot Status for Y-Potentiometer 2 Joystick B One-Shot Status for X-Potentiometer 1 Joystick A One-Shot Status for Y-Potentiometer 0 Joystick A One-Shot Status for X-Potentiometer I/O Port 201h – Start One-Shot ....................................... WO 7-0 (Value Written is Ignored) -53- Register Descriptions - Super-I/O I/O Ports VT82C686B ...
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... Register Number Used to select a specific DWORD in the device’s configuration space ........................................ always reads 0 1-0 Fixed Port CFF-CFC - Configuration Data .............................. RW Revision 1.71 June 9, 2000 There are 7 “functions” implemented in the VT82C686B: Function # Function 0 PCI to ISA Bridge 1 IDE Controller 2 USB Controller Ports 0-1 3 ...
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... Function 0 Registers - PCI to ISA Bridge All registers are located in the function 0 PCI configuration space of the VT82C686B. These registers are accessed through PCI configuration mechanism #1 via I/O address CF8/CFC. PCI Configuration Space Header Offset 1-0 - Vendor ID = 1106h ......................................... RO Offset 3-2 - Device ID = 0686h .......................................... RO Offset 5-4 - Command ....................................................... RW 15-8 Reserved ...
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... DMA type F Timing on Channel 6............default=0 4 DMA type F Timing on Channel 5............default=0 3 DMA type F Timing on Channel 3............default=0 2 DMA type F Timing on Channel 2............default=0 1 DMA type F Timing on Channel 1............default=0 0 DMA type F Timing on Channel 0............default=0 Note: For bits 0-6 above, see also Rx41[3] -56- Function 0 Registers - PCI to ISA Bridge VT82C686B ...
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... Write Delay Transaction Time-Out Timer 0 Disable................................................... default 1 Enable 1 Read Delay Transaction Time-Out Timer 0 Disable................................................... default 1 Enable Software PCI Reset ......write 1 to generate PCI reset 0 -57- Function 0 Registers - PCI to ISA Bridge VT82C686B Write" function is ...
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... Forward D8000-DBFFF Accesses to PCI ......def=0 5 Forward D4000-D7FFF Accesses to PCI .......def=0 4 Forward D0000-D3FFF Accesses to PCI .......def=0 3 Forward CC000-CFFFF Accesses to PCI .....def=0 2 Forward C8000-CBFFF Accesses to PCI ......def=0 1 Forward C4000-C7FFF Accesses to PCI .......def=0 0 Forward C0000-C3FFF Accesses to PCI .......def=0 -58- Function 0 Registers - PCI to ISA Bridge VT82C686B ...
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... Enable 3 MC97 IRQ to APIC[23:16] with Rx3C[2:0] 0 Disable................................................... default 1 Enable 2 AC97 IRQ to APIC[23:16] with Rx3C[2:0] 0 Disable................................................... default 1 Enable 1 USB Port 1 IRQ to APIC[23:16] with Rx3C[2:0] 0 Disable................................................... default 1 Enable 0 USB Port 0 IRQ to APIC[23:16] with Rx3C[2:0] 0 Disable................................................... default 1 Enable -59- Function 0 Registers - PCI to ISA Bridge VT82C686B ...
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... APIC Connection 0 APIC on SD Bus.................................... default 1 APIC on XD Bus 1 Reserved (Do Not Program) ....................default = 0 0 DMA Line Buffer Disable 0 DMA cycles can be to/from line buffer ....... def 1 Disable DMA Line Buffer -60- Function 0 Registers - PCI to ISA Bridge VT82C686B If the internal RTC is ...
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... Channel 6 Base Address Bits 15-4...........default = 0 3 Channel 6 Enable 0 Disable................................................... default 1 Enable 2-0 Reserved ........................................always reads 0 Offset 6F-6E - Distributed DMA Ch 7 Base / Enable .... RW 15-4 Channel 7 Base Address Bits 15-4...........default = 0 3 Channel 7 Enable 0 Disable................................................... default 1 Enable 2-0 Reserved ........................................always reads 0 -61- Function 0 Registers - PCI to ISA Bridge VT82C686B ...
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... GPO25 Enable (Pin G5) 0 See bit-3 & Rx76[7-6] for G5 pin function.. def 1 Pin G5 defined as GPO25 1 GPO24 Enable (Pin H3) 0 See bit-3 & Rx68[3] for H3 pin function..... def 1 Pin H3 defined as GPO24 0 Positive Decode 0 Subtractive Decode................................ default 1 Positive Decode -62- Function 0 Registers - PCI to ISA Bridge VT82C686B ...
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... APICD1)................................................ default 3 IRQ0 Output 0 Disable................................................... default 1 Enable IRQ0 output to GPIOC 2 RTC Rx32 Write Protect 0 Disable................................................... default 1 Enable 1 RTC Rx0D Write Protect 0 Disable................................................... default 1 Enable 0 GPO13 Enable (Pin U5) 0 Pin defined as SOE# .............................. default 1 Pin defined as GPO13 -63- Function 0 Registers - PCI to ISA Bridge VT82C686B ...
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... Offset 7F-7E – 32-Bit DMA Control ............................... RW 15-3 32-Bit DMA High Page (A31-24) Registers IOBase 2-1 Reserved ........................................always reads 0 0 32-Bit DMA 0 Disable................................................... default 1 Enable Offset 80 – Programmable Chip Select Mask ................ RW 7-4 PCS1# I/O Port Address Mask [3-0] 3-0 PCS0# I/O Port Address Mask [3-0] -64- Function 0 Registers - PCI to ISA Bridge VT82C686B ...
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... Reserved ........................................always reads 0 FDC Decoding Range 0 Primary .................................................. default 1 Secondary Sound Blaster Positive Decoding 0 Disable................................................... default 1 Enable Sound Blaster Decode Range 00 220h-22Fh, 230h-233h .......................... default 01 240h-24Fh, 250h-253h 10 260h-26Fh, 270h-273h 11 280h-28Fh, 290h-293h Function 0 Registers - PCI to ISA Bridge VT82C686B ...
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... Disable 2 Function 5 Audio 0 Enable.....................................................default 1 Disable 1 Super-I/O Configuration 0 Disable ...................................................default 1 Enable 0 Super-I/O 0 Disable ...................................................default 1 Enable Revision 1.71 June 9, 2000 Offset 86 – PNP IRQ/DRQ Test 1 (Do Not Program) ... RW Offset 87 – PNP IRQ/DRQ Test 2 (Do Not Program) ... RW -66- Function 0 Registers - PCI to ISA Bridge VT82C686B ...
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... Disable................................................... default 1 Enable 3 PCS3# 0 Disable................................................... default 1 Enable 2 PCS2# 0 Disable................................................... default 1 Enable 1 PCS1# 0 Disable................................................... default 1 Enable 0 PCS0# 0 Disable................................................... default 1 Enable Offset 8D-8C – PCS2# I/O Port Address ........................ RW 15-0 PCS2# I/O Port Address Offset 8F-8E – PCS3# I/O Port Address ......................... RW 15-0 PCS3# I/O Port Address -67- Function 0 Registers - PCI to ISA Bridge VT82C686B ...
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... PCI configuration registers and Bus Master IDE I/O registers. The PCI configuration registers are located in the function 1 PCI configuration space of the VT82C686B. The Bus Master IDE I/O registers are defined in the SFF8038i v1.0 specification. PCI Configuration Space Header Offset 1-0 - Vendor ID (1106h=VIA) ................................ RO Offset 3-2 - Device ID (0571h=IDE Controller) ...
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... Offset 34 - Capability Pointer (C0h) ................................ RO Offset 3C - Interrupt Line (0Eh) ...................................... RO Offset 3D - Interrupt Pin (00h) ......................................... RO 7-0 Interrupt Routing Mode 00h Legacy mode interrupt routing............... default 01h Native mode interrupt routing Offset 3E - Min Gnt (00h) ................................................. RO Offset 3F - Max Latency (00h).......................................... RO -69- Function 1 Registers - Enhanced IDE Controller VT82C686B ...
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... Enable FIFO flush for Read DMA when interrupt asserts primary channel. .......... default 6 Secondary Channel Read DMA FIFO Flush 0 Disable 1 Enable FIFO flush for Read DMA when interrupt asserts secondary channel........ default 5-0 Reserved ........................................always reads 0 -70- Function 1 Registers - Enhanced IDE Controller VT82C686B ...
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... Sec Drive 1 Cabal Type Reporting 0 Disable................................................... default 1 Enable 3 Reserved ........................................always reads 0 2-0 Sec Drive 1 Cycle Time ......... (see above for default) Each byte defines UltraDMA operation for the indicated drive. The bit definitions are the same within each byte. -71- Function 1 Registers - Enhanced IDE Controller VT82C686B ...
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... Enable.....................................................default 1 Disable Revision 1.71 June 9, 2000 Offset 61-60 - Primary Sector Size (0200h) .................... RW 15-12 Reserved ........................................always reads 0 11-0 Number of Bytes Per Sector ...def=200h (512 bytes) Offset 69-68 - Secondary Sector Size (0200h) ................. RW 15-12 Reserved ........................................always reads 0 11-0 Number of Bytes Per Sector ...def=200h (512 bytes) -72- Function 1 Registers - Enhanced IDE Controller VT82C686B ...
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... Post Write Buffer Status 4 DMA Read Prefetch Status 3 DMA Write Prefetch Status 2 S/G Operation Complete 1 FIFO Empty Status 0 Response to External DMAREQ Offset 79 - Secondary Interrupt Control ........................ RW 7-1 Reserved ........................................always reads 0 0 Flush FIFO Before Generating IDE Interrupt 0 Disable................................................... default 1 Enable -73- Function 1 Registers - Enhanced IDE Controller VT82C686B ...
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... Refer to the SFF 8038I v1.0 specification for further details. I/O Offset 0 - Primary Channel Command I/O Offset 2 - Primary Channel Status I/O Offset 4-7 - Primary Channel PRD Table Address I/O Offset 8 - Secondary Channel Command I/O Offset A - Secondary Channel Status I/O Offset C-F - Secondary Channel PRD Table Address -74- Function 1 Registers - Enhanced IDE Controller VT82C686B ...
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... PCI configuration registers and USB I/O registers. The PCI configuration registers are located in the function 2 PCI configuration space of the VT82C686B. The USB I/O registers are defined in UHCI specification v1.1. The registers in this function control USB ports 0-1 (see function 3 for ports 2-3). PCI Configuration Space Header Offset 1-0 - Vendor ID ...
Page 82
... Set trap 60/64 status bits without checking enable bits 1 A20gate Pass Through Option 0 Pass through A20GATE command sequence defined in UHCI .................................... default 1 Don’t pass through Write I/O port 64 (ff) 0 USB IRQ Test Mode 0 Normal Operation .................................. default 1 Generate USB IRQ -76- Function 2 Registers - USB Controller Ports 0-1 VT82C686B ...
Page 83
... Refer to the UHCI v1.1 specification for further details. I/O Offset 1-0 - USB Command I/O Offset 3-2 - USB Status I/O Offset 5-4 - USB Interrupt Enable I/O Offset 7-6 - Frame Number I/O Offset B-8 - Frame List Base Address I/O Offset 0C - Start Of Frame Modify I/O Offset 11-10 - Port 0 Status / Control I/O Offset 13-12 - Port 1 Status / Control -77- Function 2 Registers - USB Controller Ports 0-1 VT82C686B ...
Page 84
... PCI configuration registers and USB I/O registers. The PCI configuration registers are located in the function 3 PCI configuration space of the VT82C686B. The USB I/O registers are defined in UHCI specification v1.1. The registers in this function control USB ports 2-3 (see function 2 for ports 0-1). PCI Configuration Space Header Offset 1-0 - Vendor ID ...
Page 85
... Set trap 60/64 status bits without checking enable bits 1 A20gate Pass Through Option 0 Pass through A20GATE command sequence defined in UHCI .................................... default 1 Don’t pass through Write I/O port 64 (ff) 0 USB IRQ Test Mode 0 Normal Operation .................................. default 1 Generate USB IRQ -79- Function 3 Registers - USB Controller Ports 2-3 VT82C686B ...
Page 86
... Refer to the UHCI v1.1 specification for further details. I/O Offset 1-0 - USB Command I/O Offset 3-2 - USB Status I/O Offset 5-4 - USB Interrupt Enable I/O Offset 7-6 - Frame Number I/O Offset B-8 - Frame List Base Address I/O Offset 0C - Start Of Frame Modify I/O Offset 11-10 - Port 0 Status / Control I/O Offset 13-12 - Port 1 Status / Control -80- Function 3 Registers - USB Controller Ports 2-3 VT82C686B ...
Page 87
... This section describes the ACPI (Advanced Configuration and Power Interface) Power Management VT82C686B which includes a System Management Bus (SMBus) interface controller and Hardware Monitoring (HWM) subsystem. The power management system of the VT82C686B supports both ACPI and legacy power management functions and is compatible with the APM v1.2 and ACPI v1 ...
Page 88
... Timer........................................... default 1 32-bit Timer 2 RTC Enable Signal Gated with PSON (SUSC#) in Soft-Off Mode 0 Disable................................................... default 1 Enable 1 STPCLK Timer Tick Base Select 0 30 usec ................................................... default 1 1 msec 0 DEVSEL# Test Mode (Do Not Program).......def = 0 -82- Function 4 Regs - Power Management, SMBus and HWM VT82C686B The ...
Page 89
... Ena/Disa IRQ6 as Secondary Intr Channel 5 1/0 = Ena/Disa IRQ5 as Secondary Intr Channel 4 1/0 = Ena/Disa IRQ4 as Secondary Intr Channel 3 1/0 = Ena/Disa IRQ3 as Secondary Intr Channel 2 Reserved ........................................always reads 0 1 1/0 = Ena/Disa IRQ1 as Secondary Intr Channel 0 1/0 = Ena/Disa IRQ0 as Secondary Intr Channel -83- Function 4 Regs - Power Management, SMBus and HWM VT82C686B ...
Page 90
... Disable................................................... default 1 Enable SMI Level Output (Low) 0 Disable................................................... default 1 Enable (set this bit for socket-370 coppermine) Internal Clock Stop for PCI Idle 0 Disable................................................... default 1 Enable Internal Clock Stop During C3 0 Disable................................................... default 1 Enable Internal Clock Stop During Suspend 0 Disable................................................... default 1 Enable VT82C686B ...
Page 91
... GP0 Timer Automatic Reload 0 1 1-0 GP0 Timer Base 00 Disable................................................... default 01 1/16 second 10 1 second 11 1 minute Register (Power -85- Function 4 Regs - Power Management, SMBus and HWM VT82C686B Timer Reload Enable Register GP0 Timer stops at 0 ............................ default Reload GP0 timer automatically after counting down to 0 (Power ...
Page 92
... Deassert SUSST1# Before PWRGD Rising for S5 Wakeup 0 Disable................................................... default 1 Enable ........................................always reads 0 1 Reserved 0 USB Wakeup for STR/STD/Soff 0 Disable................................................... default 1 Enable Offset 57 – Miscellaneous Control................................... RW ........................................always reads 0 7-1 Reserved 0 Internal THRM# Output on GPO21 0 Disable................................................... default 1 Enable -86- Function 4 Regs - Power Management, SMBus and HWM VT82C686B ...
Page 93
... Revision 1.71 June 9, 2000 Offset 59 – GP2 Timer ...................................................... RW 7 Write: GP2 Timer Load Value...............default = 0 Read: GP2 Timer Current Count Offset 5A – GP3 Timer ..................................................... RW 7 Write: GP3 Timer Load Value...............default = 0 Read: GP3 Timer Current Count -87- Function 4 Regs - Power Management, SMBus and HWM VT82C686B ...
Page 94
... Code) may be changed by writing the desired value to this location. Offset 63 - Base Class Read Value .................................. WO 7-0 Rx0B Read Value The value returned by the register at offset 0Bh (Base Class Code) may be changed by writing the desired value to this location. Revision 1.71 June 9, 2000 -88- Function 4 Regs - Power Management, SMBus and HWM VT82C686B ...
Page 95
... Bit-0 must be set to 0 for proper operation Offset D5 – SMBus Slave Address for Port 2 ................. RW 7-0 SMBus Slave Address for Port 2...............default=0 Bit-0 must be set to 0 for proper operation Offset D6 – SMBus Revision ID ....................................... RO 7-0 SMBus Revision Code -89- Function 4 Regs - Power Management, SMBus and HWM VT82C686B ...
Page 96
... GBL_STS bit is set. Reserved ........................................always reads 0 ........................................always reads 0 Reserved ACPI Timer Enable (TMR_EN) ..............default = 0 This bit may be set to trigger either an SCI or an SMI (depending on the setting of the SCI_EN bit generated when the TMR_STS bit is set. Power Management I/O-Space Registers VT82C686B ...
Page 97
... S0 (working) system state. The timer is reset to an initial value of zero during a reset, and then continues counting until the 14.31818 MHz input to the chip is stopped. If the clock is restarted without a reset, then the counter will continue counting from where it stopped. -91- Power Management I/O-Space Registers VT82C686B ...
Page 98
... Level 2 Reads from this register put the processor into the Stop Grant state (the VT82C686B asserts STPCLK# to suspend the processor). Wake up from Stop Grant state is by interrupt (INTR, SMI, and SCI). Reads from this register return all zeros; writes to this register have no effect ...
Page 99
... Enable SMI on setting of the GPI16_STS bit.def=0 1 Enable SMI on setting of the GPI1_STS bit...def=0 0 Enable SMI on setting of the EXT_STS bit....def=0 These bits allow generation of an SMI using a separate set of conditions from those used for generating an SCI. -93- Power Management I/O-Space Registers VT82C686B ...
Page 100
... SMI on Secondary Event Timer Time Out (STTO_EN) ......................................................def=0 This bit may be set to trigger an SMI to be generated when the STTO_STS bit is set. 0 SMI on Primary Activity (PACT_EN) ...........def=0 This bit may be set to trigger an SMI to be generated when the PACT_STS bit is set. -94- VT82C686B ........................................always reads 0 Power Management I/O-Space Registers ...
Page 101
... Revision 1.71 June 9, 2000 I/O Offset 2F - SMI Command (SMI_CMD) ................. RW 7-0 from suspend when -95- SMI Command Writing to this port sets the SW_SMI_STS bit. Note that if the SW_SMI_EN bit is set (see bit-6 of the Global Enable register at offset 2Ah), then an SMI is generated. Power Management I/O-Space Registers VT82C686B ...
Page 102
... Don't set PACT_STS if PIDE_STS is set.... def 1 Set PACT_STS if PIDE_STS is set 1 SMI on Primary INTR Status .............. (PIRQ_EN) 0 Don't set PACT_STS if PIRQ_STS is set.... def 1 Set PACT_STS if PIRQ_STS is set 0 SMI on PCI Master Status .................... (DRQ_EN) 0 Don't set PACT_STS if DRQ_STS is set .... def 1 Set PACT_STS if DRQ_STS is set -96- Power Management I/O-Space Registers VT82C686B ...
Page 103
... SMI on BIOS Write............................... (BWR_EN 3-2 Reserved 1 SMI on GPIO Range 3 Access..............(GPR3_EN SMI on GPIO Range 2 Access..............(GPR2_EN SIDE_STS, or -97- VT82C686B ......................................... always read 0 ......................................... always read 0 ......................................... always read 0 Disable................................................... default Enable ......................................... always read 0 Disable................................................... default Enable Disable................................................... default Enable Power Management I/O-Space Registers ...
Page 104
... GPI[23-16] by Refresh Scan .................... Read Only ......................................... always read 0 15-12 Reserved 11-0 GPI[11-0] Input Value ............................. Read Only I/O Offset 4F-4C - GPO Port Output Value (GPOVAL) RW Reads from this register return the last value written (held on chip) ........................................always reads 0 31-26 Reserved 25-0 GPO[25-0] Output Value................def = 3FFFFFFh -98- Power Management I/O-Space Registers VT82C686B ...
Page 105
... Reserved ........................................always reads 0 Slave Busy ......................................................... RO 0 SMBus controller slave interface is not processing data ...................................... default 1 SMBus controller slave interface is busy receiving data. None of the other SMBus registers should be accessed if this bit is set. System Management Bus I/O-Space Registers VT82C686B ...
Page 106
... It is reset reads of the SMBus Host Control register (I/O Offset 2) and incremented automatically by each access to this register. The transfer of block data into (read) or out of (write) this storage array during an SMBus transaction always starts at index address 0. SMBUS Block Data ..................................default = 0 7-0 -100- System Management Bus I/O-Space Registers VT82C686B ...
Page 107
... SMBus Slave Data ....................................default = 0 This field contains the data value which was transmitted during an external SMBus master access whose address field matched one of the slave shadow port addresses or the SMBus host controller slave port address of 10h. -101- System Management Bus I/O-Space Registers VT82C686B ...
Page 108
... One consequence of the above is that if high limits are set to all ones (FFh or 11111111b), interrupts are disabled for high limits (i.e., interrupts will only be generated for cases when voltages are equal to or below the low limits). -102- Hardware Monitor I/O Space Registers VT82C686B ...
Page 109
... Revision 1.71 June 9, 2000 Temperature Resolution All high and low limits -103- VT82C686B Hardware Monitor I/O Space Registers ...
Page 110
... Chassis Error Mask 3 TSENS2 Temperature Error Mask 2-1 Reserved 0 VSENS4 Voltage Error Mask (12V) -104- VT82C686B 0 Enable interrupt on error status bit set ......... def 1 Disable interrupt on error status bit set 0 Enable interrupt on error status bit set ......... def 1 Disable interrupt on error status bit set ...
Page 111
... Comparator mode. An interrupt occurs if the temperature goes above the hot limit. This interrupt remains active until the temperature goes below the hot limit (i.e., no hysteresis). 11 Default Interrupt Mode (same as 00) -105- Hardware Monitor I/O Space Registers VT82C686B An interrupt is ...
Page 112
... SoundBlaster Pro. There are two sets of software accessible registers: PCI configuration registers and I/O registers. The PCI configuration registers for the Audio Codec are located in the function 5 PCI configuration space of the VT82C686B. The PCI configuration registers for the Modem Codec are located in the function 6 PCI configuration space. The I/O registers are located in the system I/O space. PCI Configuration Space Header – ...
Page 113
... IRQ6 0111 IRQ7 1000 IRQ8 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 IRQ13 1110 IRQ14 1111 Disable Offset 3D - Interrupt Pin (03h) ......................................... RO Offset 3E - Minimum Grant (00h) .................................... RO Offset 3F - Minimum Latency (00h) ................................. RO -107- Function 5 & 6 Registers - AC97 Audio & Modem Codecs VT82C686B ...
Page 114
... AC Link FM Channel PCM Data Out (SELFM) 0 Disable................................................... default 1 Enable Bit valid in function 5 only (reserved in function Link SB PCM Data Output (SELSB) 0 Disable................................................... default 1 Enable Bit valid in function 5 only (reserved in function 6) -108- Function 5 & 6 Registers - AC97 Audio & Modem Codecs VT82C686B ...
Page 115
... Route FM Trap interrupt to NMI........... default 1 Route FM Trap interrupt to SMI 1 FM SGD Data for SoundBlaster Mixing 0 Disable................................................... default 1 Enable 0 FM Trap Interrupt 0 Enable 1 Disable .................................................. default Offset 4B-4A – Game Port Base Address ....................... RW 15-0 Game Port Base Address .........................default = 0 -109- Function 5 & 6 Registers - AC97 Audio & Modem Codecs VT82C686B ...
Page 116
... End Of Link. 1 indicates this block is the last of the link. If the channel “Interrupt on EOL” bit is set, then an interrupt is generated at the end of the transfer. block. If the channel “Interrupt on FLAG” bit is set, then an interrupt is generated at the end of this block. block. To resume the transfer, write 1 to Rx?0[2]. VT82C686B ...
Page 117
... I/O Offset 27-24 – FM SGD Rd Ch Table Pointer Base RW 31-0 SGD Table Pointer Base Address (even addr).....W Current Pointer Address ........................................R I/O Offset 2F-2C – FM SGD Rd Chan Current Count ... RO ........................................ always reads 0 31-24 Reserved 23-0 Current SGD FM Read Channel Count Revision 1.71 June 9, 2000 -111- Function 5 & 6 Registers - AC97 Audio & Modem Codecs VT82C686B ...
Page 118
... End Of Link. 1 indicates this block is the last of the link. If the channel “Interrupt on EOL” bit is set, then an interrupt is generated at the end of the transfer. block. If the channel “Interrupt on FLAG” bit is set, then an interrupt is generated at the end of this block. block. To resume the transfer, write 1 to Rx?0[2]. VT82C686B ...
Page 119
... R GPI[15-0] Interrupt Status clear 15-0 Codec GPIO .........................................................RW R Reflect status of Codec GPI[15-0] W Triggers AC-Link slot-12 output to codec Offset 8F-8C – Codec GPI Interrupt Enable ................. RW 31-16 Interrupt on GPI[15-0] Change of Status..........RW 0 Disable 1 Enable 15-0 Reserved ........................................always reads 0 -113- Function 5 & 6 Registers - AC97 Audio & Modem Codecs VT82C686B ...
Page 120
... I/O Offset 80-FFh – Secondary Codec Shadow .............. RW The content of these registers is updated when writing data to secondary codec registers 0-7Fh or when valid secondary codec register status is returned. -114- Function 5 & 6 Registers - AC97 Audio & Modem Codecs VT82C686B ...
Page 121
... APIC Version.................................. always reads 11h 7-0 The implementation version for this APIC is 11h. Offset 2 – APIC Arbitration (0000 0000h) ...................... RO 31-28 Reserved .................................... always reads 00h 27-24 APIC Arbitration ID ...................... always reads 00h 23-0 Reserved .................................... always reads 00h -115- Function 5 & 6 Registers - AC97 Audio & Modem Codecs VT82C686B ...
Page 122
... Logical Mode 010 SMI 011 -reserved- 100 NMI 101 INIT 110 -reserved- 111 External INT 7-0 Interrupt Vector Contains the interrupt vector for this interrupt. Vector values range from 10h to FEh. -116- Function 5 & 6 Registers - AC97 Audio & Modem Codecs VT82C686B ...
Page 123
... Figure 6. Power Management Subsystem Block Diagram Refer to ACPI Specification v1.0 and APM specification v1.2 for additional information. Revision 1.71 June 9, 2000 Processor Bus States The VT82C686B supports the complete set processor states as specified in the Advanced Configuration and Power Interface (ACPI) specification (and defined in ACPI I/O space Registers 10-15): C0: ...
Page 124
... POS (only SUSA# asserted), to STR (both SUSA# and SUSB# asserted), and to STD (all three SUS# signals asserted). In particular, the assertion of SUSC# can be used to turn off the VCC supply to the VT82C686B. One additional suspend status indicator (SUSST1#) is provided to inform the north bridge and the rest of the system of the processor and system suspend states ...
Page 125
... PCKRUN# PCI Bus PCLK BIOS ROM Keyboard / Mouse Figure 7. System Block Diagram Using the VT82C686B Super South Bridge Revision 1.71 June 9, 2000 3) Generic Global Events defined in the GBL_STS and System and Processor Resume Events Depending on the system suspend state, different features can be enabled to resume the system ...
Page 126
... Peripheral Events Primary and secondary events define system events in general and the response is typically expressed in terms of system events. Individual peripheral events can also be monitored by the VT82C686B through the GP1 timer. The following four categories of peripheral events are distinguished (via register GP_RLD_EN): Bit-7 ...
Page 127
... SUS Volts V USB Volts V HWM Volts V BAT Volts FERR#, USBCLK, PWRBTN#, EXTSMI#, BATLOW#, FAN1, FAN2, SMBCLK, SMBDATA Volts All other inputs =3.3V +0.3/-1.3V, GND=0V Unit Condition 4.0mA -1.0mA < V < 0.45 < V < V OUT CC mA Electrical Specifications VT82C686B ...
Page 128
... Figure 8. Mechanical Specifications – 352 Pin Ball Grid Array Package Revision 1.71 June 9, 2000 M S ECHANICAL PECIFICATIONS 24.00 Ref -122- VT82C686B Ø 1.00 (3X) Ref. Ø 0.75±0.15 (352X) Package Mechanical Specifications ...