CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 124

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

Register 8: Primary IDE Control Address Register (Read/Write)
Note: Register Indices 18H-1FH will return all zeroes when read.
Register 9: Primary Bus Master IDE Control Address Register (Read/Write)
Register 10: Primary IDE Interrupt INTA Control Register (Read/Write)
Register 11: Primary IDE Interrupt Pin Control Register (Read Only)
Note: Register Indices 3EH-3FH will return all zeroes when read.
Bit
31:0
Bit
31:0
Bit
7:0
Bit
7:0
Function
Primary IDE Control Address Register:
This register specifies the amount of I/O space required for the primary IDE control registers.
The IDE control block requires 2 bytes of I/O space (Bits [1:0] are hardwired to 01). Bits [15:2]
are programmable. Bits [31:16] are hard-wired to 0000H. See stand-alone description for
32-bit decode option.
Function
Bus Master IDE Control Address Register:
This register specifies the amount of I/O space required for the bus master IDE control
registers. The bus master IDE control block requires 16 bytes of I/O space (Bits [3:0] are
hardwired to 0001). Bits [15:4] are programmable. Bits [31:16] are hard-wired to 0000H. See
stand-alone description for 32-bit decode option.
Function
Primary IDE Interrupt Control Register:
This register is written by the POST software to inform the system which interrupt level the
primary IDE controller is connected.
Function
Primary IDE Interrupt Pin Control Register:
01H:
The Primary IDE Channel Interrupt is connected to PCI INTA internally.
PRELIMINARY
124
Index=14H with a 32-bit access
Index=3DH with an 8-bit access
Index=3CH with an 8-bit access
Index=20H with a 32-bit access
CY82C693UB
Default
00000000H
Default
00000000H
Default
14H
Default
01H