CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 28

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

ISA Interface Signals (continued)
Name
XD6/IDEIRQ1
GPIO1/BUSY
XD5/IREQ0
XD4/IACK0
XD3/IREQ1
XD2/IACK1
XD1/XDEN
XD0/XDIR
LA23/IDECS0
LA22/IDECS1
LA21/SIDECS0
LA20/SIDECS1
LA[19:17]/
IDEA[2:0]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRELIMINARY
Description
XD Bus, Bit 6/Programmable Interrupt Request 1/General Purpose I/O 1/PCI Bus
Busy: If zero TTL is desired for XD bus support (BIOS ROM data, external keyboard
controller data, and external RTC data), this is bit 6 of the data bus. Otherwise, this is
user-selectable to provide support for a Programmable Interrupt Request or a general
purpose I/O. As a GPIO, this signal can either reflect the contents of an internal register
bit (output) or set an internal register bit to the value driven on the line (input).
If pin 179 is strapped LOW during power-up (GNTBSY split), this signal becomes the
BUSY input. BUSY is asserted by the CPU-to-PCI bridge to tell the PCI arbiter in the
CY82C693UB that the PCI bus is currently busy and may not be granted to any other
PCI master.
XD Bus, Bit 5/IDE DMA Request 0: If zero TTL is desired for XD bus support (BIOS
ROM data, external keyboard controller data, and external RTC data), this is bit 5 of
the data bus. Otherwise, this is user-selectable to provide support for IDE DMA.. For
IDE DMA support, this signal is DMA request 0 (primary IDE channel DMA request).
XD Bus, Bit 4/IDE DMA Acknowledge 0: If zero TTL is desired for XD bus support
(BIOS ROM data, external keyboard controller data, and external RTC data), this is bit
4 of the data bus. Otherwise, this is user-selectable to provide support for IDE DMA.
For IDE DMA support, this signal is DMA acknowledge 0 (primary IDE channel DMA
acknowledge)..
XD Bus, Bit 3/IDE DMA Request 1: If zero TTL is desired for XD bus support (BIOS
ROM data, external keyboard controller data, and external RTC data), this is bit 3 of
the data bus. Otherwise, this is user-selectable to provide support for IDE DMA. For
IDE DMA support, this signal is DMA request 1 (secondary IDE channel DMA request).
XD Bus, Bit 2/IDE DMA Acknowledge 1: If zero TTL is desired for XD bus support
(BIOS ROM data, external keyboard controller data, and external RTC data), this is bit
2 of the data bus. Otherwise, this is user-selectable to provide support for IDE DMA or
a general purpose I/O. For IDE DMA support, this signal is DMA acknowledge 1 (sec-
ondary IDE channel DMA acknowledge). As a GPIO, this signal can either reflect the
contents of an internal register bit (output) or set an internal register bit to the value
driven on the line (input).
XD Bus, Bit 1/External XD Bus Buffer Enable: If zero TTL is desired for XD bus support
(BIOS ROM data, external keyboard controller data, and external RTC data), this is bit
1 of the data bus. Otherwise, this pin provides the enable for a buffer between XD[7:0]
and SD[7:0].
XD Bus, Bit 0/External XD Bus Direction Control: If zero TTL is desired for XD bus
support (BIOS ROM data, external keyboard controller data, and external RTC data),
this is bit 0 of the data bus. Otherwise, this pin provides the direction control for a buffer
between XD[7:0] and SD[7:0].
Latched Address 23/ IDE Chip Select0: This signal connects to LA23 on the ISA bus
and is used to provide access up to 16 MB. During IDE accesses, this signal provides
the chip select 0 for the primary channel.
Latched Address 22/ IDE Chip Select1: This signal connects to LA22 on the ISA bus
and is used to provide access up to 16 MB. During IDE accesses, this signal provides
the chip select 1 for the primary channel.
Latched Address 21/ Secondary IDE Chip Select0: This signal connects to LA21 on
the ISA bus and is used to provide access up to 16 MB. During IDE accesses, this
signal provides the chip select 0 for the secondary channel.
Latched Address 20/ Secondary IDE Chip Select1: This signal connects to LA20 on
the ISA bus and is used to provide access up to 16 MB. During IDE accesses, this
signal provides the chip select 1 for the secondary channel.
Latched Address 19 Through 17/ PCI IDE Register Select Address 2 Through 0: These
signals connect to LA19 through LA17 on the ISA bus and are used to provide access
up to 16 MB. During IDE accesses, these signals provide the register select (or ad-
dress) to the IDE connectors.
28
CY82C693UB