CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 72

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

CY82C693UB DMA Controller Registers
There are two DMA controllers cascaded together inside the
CY82C693UB. (DMAC1 and DMAC2). Each DMA Controller
contains four channels. DMAC1 controls the 8-bit DMA oper-
ations and DMAC2 controls 16-bit DMA operations. Channel
0 of DMAC2 provides the cascade between the two control-
lers, and therefore, may not be used for DMA data transfers.
DMAC1’s DMA request and acknowledge signals correspond
to
DMAC2’s DMA request and acknowledge signals correspond
to the DREQ5–DREQ7 and DACK5–DACK7 signals.
The internal registers for the CY82C693UB DMA controllers
are defined in this section. The registers can be accessed by
performing I/O reads and writes to Addresses 000H through
00FH (for DMAC1) and Addresses 0C0H through 0CFH (for
DMAC2). The DMA Page (Upper Order DMA address bits are
controlled using I/O addresses 080H–08FH). All DMAC regis-
ters are eight bits (1 byte) wide. Performing I/O accesses to
these address ranges will place the corresponding DMA con-
troller into its Program State.
The DMA controller register address space has been in-
creased using an additional address flip-flop. The flip-flop tog-
gles every time an access occurs to the DMA word count or
DMA address registers. The flip-flop is cleared by the asser-
tion of the CPURST signal (from the CY82C693UB) or a MAS-
TER CLEAR from the DMA registers. The flip-flop can also be
programmed by an access to the flip-flop control register.
The DMA channels within the controllers should be masked
prior to entering the Program State to insure that a DMA ac-
cess is not attempted to a partially programmed channel.
After the DMA controllers are programmed, they should be
unmasked. This will allow the DMA controllers to enter the
DMA Register 0: DMAC1 Channel 0 Current Address Register (Read/Write) - I/O Address=000H
DMA Register 1: DMAC1 Channel 0 Current Word Count Register (Read/Write) - I/O Address=001H
DMA Register 2: DMAC1 Channel 1 Current Address Register (Read/Write) - I/O Address=002H
I/O Read I/O Write Flip-Flop State Function
I/O Read I/O Write Flip-Flop State Function
I/O Read I/O Write Flip-Flop State Function
0
0
1
1
0
0
1
1
0
0
1
1
the
DREQ0–DREQ3
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
and
DACK0–DACK3
Read Low Byte of Current Address Register
Read High Byte of Current Address Register
Write Low Byte of Base Address Register and Current Address Register
Write High Byte of Base Address Register and Current Address Register
Read Low Byte of Current Word Count Register
Read High Byte of Current Word Count Register
Write Low Byte of Base Word Count Register and Current Word Count Register
Write High Byte of Base Word Count Register and Current Word Count Register
Read Low Byte of Current Address Register
Read High Byte of Current Address Register
Write Low Byte of Base Address Register and Current Address Register
Write High Byte of Base Address Register and Current Address Register
PRELIMINARY
signals.
72
ACTIVE State. The ACTIVE State will be entered when a valid
DMA request is recognized by the CY82C693UB. During 8-bit
DMA transfers, DMAC1 places the memory address bits on
Address 0 through 15. For 16-bit DMA transfers, DMAC2 plac-
es the memory address bits on Address 1 through 16 (Address
0 is zero for 16-bit transfers). The page address bits are placed
on Address 17 through 23.
DMA registers 0 through 7 provide access to each channel’s
Current Address Register, Current Word Count Register, Base
Address Register, and Base Word Count Register. The Cur-
rent Address Register contains the 16-bit address used during
transfers. The value in the Current Address Register is either
incremented or decremented (programmable) to provide the
transfer addresses. Channel 0 will hold its address (without
incrementing or decrementing) by setting the Address Hold Bit
in the Command Register. If Autoinitializtion is selected, the
Current Address Register is reloaded with the contents of the
Base Address Register when the terminal count is reached in
the Current Word Count Register. The Current Word Count
Register contains the number of transfers to perform. This reg-
ister is decremented with each transfer. The terminal count will
be reached on the transition of this register from 0000H to
FFFFH. Therefore, the actual number of transfers will be one
more than the value loaded in the Current Word Count Regis-
ter. When the terminal count is reached, the channel will be
suspended and either masked or autoinitialized. The Base Ad-
dress Register is write-only and is loaded along with the Cur-
rent Address Register. This register stores the initial value of
the Current Address Register and will reload its contents into
the Current Address Register when the terminal count is
reached if autoinitialization is selected. Likewise, the Base
Word Count Register is used to reload the Current Word Count
Register with its initial value if autoinitialization is programmed.
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CY82C693UB