CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 31

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

ISA Interface Signals (continued)
Name
DACK7/EXTBUF
/GPIO11
REFSH
SPKR
EOP
IGNNE/ROMS1
FERR
I/O
I/O
I/O
O
O
I/O
I
PRELIMINARY
Description
ISA DMA/Master 7 Acknowledged Input/Internal IDE Controller Enable/General Pur-
pose I/O 11: This signal is used by the CY82C693UB to grant ISA bus mastership to
external ISA peripherals for DMA or ISA MASTER cycles. At power-up, this pin should
be pulled-down through a 1K Ohm resistor to enable a direct connection to the XD bus.
If IDE Bus Master functions are required, the pin should not be pulled down and an
external XD bus buffer should be used.
This signal can be used as a GPIO if DACK[3:0] are programmed to connect to an
external ’138 type TTL 1 of 8 decoder.
AT Refresh: Driven when an ISA refresh cycle is in progress. As an input, this signal
will force a refresh cycle to be initiated.
Speaker Output: This signal is the output of counter 2 in the timer/counter logic. It can
be used to drive a speaker.
End of Process: This signal is driven by the CY82C693UB to signal the end of a block
transfer during a DMA cycle.
Ignore Numerical Error: This signal is driven by the CY82C693UB to the CPU and
should be connected to the CPU’s IGNNE pin. When this signal is asserted, the pro-
cessor will ignore numerical errors and continue executing non-control, floating-point
instructions.
At power-up, this signal acts as ROMS1. ROMS1 is used in conjunction with ROMS0
(GTA20) and ROMMODE (ROMCS) to implement boot-block Flash recovery straps.
The strapping is defined as follows:
ROMMODE
Floating Point Error: This signal from the processor causes an IRQ13 from the
CY82C693UB to occur.
1
0
0
0
0
ROMS0
X
1
1
0
0
31
ROMS1
X
1
1
1
0
Result
No ROM address bits are
inverted. (EPROM or boot-
block recovery mode).
ROM address bit 16 is inverted
(Normal operation w/ 16Kx8
boot-block Flash)
ROM address bit 17 is inverted
(Normal operation w/ 32Kx8
boot-block Flash)
ROM address bit 18 is inverted
(Normal operation with 64Kx8
boot-block Flash)
ROM address bit 15 is inverted
(Normal operation with 8Kx8
boot-block Flash)
CY82C693UB