CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 22

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

Update cycles are performed once per second. The update
cycle increments the seconds byte and increments the min-
utes byte on an overflow (followed by hour, day, month, year,
etc.). Alarm value comparisons are also made. During the up-
date cycle, data is undefined. However, the CY82C693UB
contains an UIP (update in progress) bit to inform the system
of updates. If the processor, upon polling the appropriate RTC
status register, sees the UIP bit set, an access to the RTC
clock data should not be performed. An update-ended inter-
rupt may also be programmed to inform the processor that the
update cycle has ended and RTC data is valid.
External RTC Control
To allow for maximum flexibility, an external RTC can be used.
The control signals for an external RTC are only used when
the internal RTC is disabled. External RTC control is only avail-
able as a bond option (separate part number). Please contact
Cypress if the use of an external RTC is desired.
Interrupt Controllers
The CY82C693UB contains two interrupt controllers (INTC1
and INTC2) that provide 82C59A functionality. There are fif-
teen separate interrupt request inputs (although some of the
interrupt requests are only available internally). The two con-
trollers are cascaded to maintain AT interrupt priorities. Inter-
rupt arbitration can be programmed to be rotating or fixed.
When interrupt requests come in from the system, the
CY82C693UB will store all requests, evaluate the priority, and
respond with the appropriate acknowledge vector for the
CPU’s first interrupt acknowledge cycle. Then, if automatic
end-of-interrupt (AEOI) is selected, the internal interrupt pend-
Accessed
Using
Ports
70H
index
and 71H
data
Ports
72H
index
and 73H
data
Figure 2. Real-Time-Clock Address Map
Seconds
Seconds Alarm
Minutes
Minutes Alarm
Hours
Hours Alarm
Day of the week
Numerical date of the month
Month
Year
RegisterA
RegisterB
RegisterC
RegisterD
114 Bytesof User-Defined
RAM
(Configuration Storage)
128 Bytes of additional User-
Defined RAM
(Configuration Storage)
Hex Address (Index)
PRELIMINARY
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
7F
80
FF
22
ing bit will be reset on the second CPU interrupt acknowledge
cycle. If AEOI is not selected, it is the responsibility of the soft-
ware to generate the appropriate end-of-interrupt (EOI) se-
quence at the end of the interrupt service routine to clear down
the interrupt (for example, if a clock interrupt is requested, the
system designer may wish the pending interrupt request to
remain active through the entire service routine. This allows
higher priority interrupts to prematurely force an exit from the
clock service routine without causing the loss of the clock in-
terrupt request. If AEOI were programmed, the request to the
CPU and the interrupt pending bit would automatically be reset
before the clock service routine was entered. If a higher priority
interrupt forced the clock routine to be exited, the clock inter-
rupt would be lost.)
The interrupt controllers (INTCs) are initialized and pro-
grammed using special command words issued by the CPU.
Initialization Command Words (ICW1 through ICW4) bring the
INTCs to a known state when the system is first powered-up
or reset. Operational Command Words (OCW1 through
OCW3) setup the various operating modes.
The following events occur automatically in the initialization
sequence:
The following options are programmable through the ICWs
and OCWs:
• The edge sense circuit is reset. Therefore, a request must
• The interrupt mask register is cleared. Interrupts are en-
• Interrupt Request (IR) 7 is set to the lowest priority on each
• Special Mask Mode is reset.
• Status Read is set to return the value in the Interrupt Re-
• Vector Mode operation: The CY82C693UB can generate
• The call address interval: The number of cycles to generate
• Edge vs. Level Sensitive Interrupt Requests: The interrupt
• Vector Address Byte: The value can be programmed.
• Automatic End-Of-Interrupt: The pending interrupt can be
• Interrupt Nesting: Interrupt nesting is a programmable op-
• Interrupt Masking: The bits of the Interrupt Mask Register
• Interrupt Priority: Priority can be programmed to be rotating
• Polling: When Polling is selected, Interrupt Requests will not
make a LOW-to-HIGH transition to be detected. If the inter-
rupt request is programmed to be edge-detected, the rising
edge must be used (LOW-to-HIGH). High-to-Low transitions
will be ignored.
abled.
INTC.
quest Register (IRR).
the vector for an interrupt acknowledge cycle.
an interrupt vector can be chosen to be 4 or 8.
request lines can be programmed to be detected on a rising
edge or a fixed level on an individual request basis.
programmed to clear automatically with the acknowledge
cycle. If AEOI is not programmed, interrupts must be cleared
within the interrupt service routine by the software.
tion. If interrupt nesting is allowed, interrupts can be assert-
ed within interrupt service routines.
can be set to mask (ignore) certain interrupt requests.
or fixed.
issue an interrupt to the CPU. They will merely set bits within
the Interrupt Pending Register (IPR). It is the responsibility
of the CPU to periodically read (poll) the IPR to determine
if an interrupt is pending.
CY82C693UB