CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 77

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

Mode Register Format. (Should be programmed for each channel.)
DMA Register 12: DMAC1 Address Space Expansion Flip-Flop Control Register (Write Only) - I/O Address=00CH
DMA Register 13: DMAC1 Master Clear Register (Write Only) - I/O Address=00DH
DMA Register 14: DMAC1 DMA Mask Clear Register (Write Only) - I/O Address=00EH
Bit
7:6
5
4
3:2
1:0
I/O Read I/O Write Flip-Flop State Function
I/O Read I/O Write Flip-Flop State Function
I/O Read I/O Write Flip-Flop State Function
0
1
0
1
0
1
1
0
1
0
1
0
Function
DMA Mode Selection Control:
00:
01:
10:
11:
See DMA Controller description for details about each mode.
Counter Direction Control:
0:
1:
Autoinitialization Control:
0:
1:
Autoinitialization will restore the initial values into the Current Address Register and Word
Count Register when the terminal count is reached. The channel will not automatically be
masked if it is autoinitialized.
DMA Transfer Type Selection Control:
00:
01:
10:
11:
See DMA Controller description for details about each transfer type.
Channel Selector:
00:
01:
10:
11:
Each DMA channel has its own mode register, but they are all accessed through I/O Address
00BH. For Mode Register writes, bits[1:0] control which channel’s mode register will be writ-
ten. To read each channel’s mode register, four sequential reads will walk through all of the
mode registers. Clearing the Mode Register Counter (DMA Register 14) will start the read
sequence at a known state (channel 0). During reads, the channel selector bits will be 11
regardless of the channel.
Demand Transfer Mode
Single Transfer Mode
Block Transfer Mode
Cascade Mode
Increment Address Counter After Each Transfer
Decrement Address Counter After Each Transfer
Disable Autoinitialization
Enable Autoinitialization
Verify Transfer
Write Transfer
Read Transfer
Undefined (DO NOT USE)
Channel 0
Channel 1
Channel 2
Channel 3
X
X
X
X
X
X
Undefined
Clear Flip-Flop (Flip-Flop=0). This is a special command. The data lines are ignored.
Undefined
Perform Master Clear. This is a special command. The data lines are ignored.
Undefined
Clear DMA Request Mask Bits (Unmask all DMA requests). This is a special command.
The data lines are ignored.
PRELIMINARY
77
CY82C693UB
Default
00
0
0
00
00