CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 20

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

Hardware power management can be selected to ease the
power-down software requirements. In the hardware power
management mode, the STOPCLK signal may be pro-
grammed to automatically assert when the suspend and/or
standby timers expire. This signal is used to reduce the power
consumption of the processors and peripherals when they are
idle.
Software power management works with CPU SMM (System
Management Mode). All Pentium-class processors have SMM
capabilities. SMM is entered through a dedicated System
Management Interrupt (SMI). SMM has its own protected ad-
dress space, which can only be accessed in System Manage-
ment Mode. All power management software should be em-
bedded in the SMI handler code stored in SMM space. SMM
memory control is handled by the CY82C691 (please see
CY82C691 datasheet). However, all SMI generation is han-
dled by the CY82C693UB.
The CY82C693UB supports Full-Speed, Standby, and Sus-
pend power-down states. Other user-defined power-down
states can be implemented. Full-Speed is the normal operat-
ing state. When power-management is enabled, the Standby
timer will begin counting. The terminal count for the Standby
timer can be set to various values between 0.2 seconds and
240 minutes. If any of the monitored events occur before the
terminal count is reached, the standby timer will reset to zero
and begin counting again. If the standby timer expires without
detecting any monitored events, the CY82C693UB will assert
SMI, allowing the SMI handler to transition the system into the
Standby state. The SMI signal must be cleared (deasserted)
by the SMI handler by performing a write to the
CY82C693UB’s internal SMI clear register (register E7H, bit
6). Once Standby state has been entered, the Suspend timer
will begin counting. The terminal counts for the suspend timer
can be set to values between 1 second and 480 minutes. If a
Standby event is detected by the CY82C693UB before the
suspend timer expires, the CY82C693UB will assert SMI, re-
set all timers (only the Suspend timer will be reset if the event
is a Suspend event), and set a status register bit to identify the
monitored event. The System Management Interrupt handler
must determine the source of the SMI by reading
CY82C693UB status registers. The handler code can use the
SMI source information to determine which state to transition
to. If the suspend timer expires before any monitored event
occurs, the CY82C693UB will once again assert SMI so that
the handler can transition to the Suspend state
The user-definable timers (User timer 1, User timer 2, and
User timer 3) can be used to create additional power-down
states. They can be enabled or disabled at any time. The user
timer terminal count values can be programmed to values be-
tween 1 second and 480 minutes. When any of the timers ex-
pire, the CY82C693UB will assert SMI (until it is cleared in the
handler) and set a configuration register bit to indicate which
timer(s) expired. The System Management Interrupt handler
must read status registers to determine the source of the SMI.
Software can then transition to any power-down state (pre-de-
fined or user-defined). Only User timer 1 is programmable to
be reset upon the detection of monitored events.
There are two power control signals used by the CY82C693UB
(STOPCLK, and EPMI). The first signal (STOPCLK) is register
controlled and can be asserted or negated in any state.
STOPCLK has been traditionally connected to the CPU’s
STOPCLK input to disable the clock to the internal CPU’s core.
When STOPCLK is enabled, it will periodically be asserted
PRELIMINARY
20
and deasserted based on programmable STOPCLK period
registers. This signal may also be used to power-down periph-
erals that support a power-down signal. External logic can
force the CY82C693UB to assert SMI by activating the EPMI
input.
The CY82C693UB contains an internal interrupt/event
counter. The terminal count for this timer should be pro-
grammed to the longest amount of time it takes to handle any
interrupt. Whenever a user-selectable event (typically an inter-
rupt) occurs, the STOPCLK signal will be deasserted for the
time period of the interrupt timer. This allows the processor to
handle the interrupt. If no other monitored events occur before
the interrupt timer expires, STOPCLK will be reasserted.
AT Refresh Logic
The CY82C693UB contains logic to support refresh cycles on
the ISA bus. An internal refresh request is generated every
15.6 microseconds. Upon detecting the refresh request, the
CY82C693UB will arbitrate for the ISA bus and generate a
refresh cycle. The CY82C693UB contains its own internal re-
fresh counter and refresh address counter. During ISA refresh
cycles, the CY82C693UB will not grant the ISA bus to any
peripheral cards. If a PCI transaction is targeting ISA, the
CY82C693UB will attempt to buffer the transaction. If the inter-
nal FIFO buffers are full or the transaction cannot be buffered,
the CY82C693UB will negate TRDY until the refresh is com-
pleted.
Pre-Read/Post-Write Buffers
There are 3 FIFOs inside the CY82C693UB. PCI/ISA FIFOs
are 1 entry deep and 32 bits wide. There is one 4 entries deep
by 32 bit wide FIFO for each IDE channel. PCI to ISA or IDE
transactions are buffered to improve system performance. ISA
or IDE transactions will likewise be buffered for transmission to
the PCI bus. PIO IDE transactions go through their own inde-
pendent buffers. The buffers eliminate some of the latency due
to arbitration for resources.
BIOS ROM Control
The CY82C693UB provides all of the control signals to sup-
port both Flash and conventional ROM. There is also a dedi-
cated XD bus to buffer the ROM data (provided IDE DMA,
Independent IDE Interrupt Requests, and several of the gen-
eral purpose I/O functions are not required). The XD bus can
also be externally buffered, which frees pins for other func-
tions. If Flash ROM is used, the CY82C693UB will provide the
write-protection through an internal Read Only register bit.
Boot-block Flash is supported through hardware strap pins.
With boot-block Flash, the boot-block can be write protected
and can be used to store recovery code (to rebuild the BIOS
from disk, network, etc.). Inverted upper address is normal
operating mode. This allows BIOS to begin in non-boot-block
memory. If the BIOS is corrupted during an update, the
CY82C693UB should be strapped to not invert the upper ROM
address bit, thus operating out of the protected boot-block
space.
Timer/Counter Logic
The CY82C693UB contains an
er/counter. It can be used to generate software time delays,
count in binary or BCD, generate interrupts, or generate
square-wave patterns. There are three independent, 16-bit
counters that can operate in the following six modes: Interrupt
CY82C693UB
8254-compatible tim-