CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 131

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

Register 12: Secondary IDE Address Setup Control Register (Read/Write)
Register 13: Secondary Master Drive IDE IOR Command Control Register (Read/Write)
Register 14: Secondary Master Drive IDE IOW Command Control Register (Read/Write)
Register 15: Secondary Slave Drive IDE IOR Command Control Register (Read/Write)
Register 16: Secondary Slave Drive IDE IOW Command Control Register (Read/Write)
Bit
31:8
7:4
3:0
Bit
7:4
3:0
Bit
7:4
3:0
Bit
7:4
3:0
Bit
7:4
3:0
Function
Reserved
Slave Drive IDE Address Setup Time:
The value programmed into this register +1 will be the setup (in PCI Clock cycles) from
address valid to IOR or IOW valid.
Master Drive IDE Address Setup Time:
The value programmed into this register +1 will be the setup (in PCI Clock cycles) from
address valid to IOR or IOW valid.
Function
16-Bit Master Drive IDE IOR Command Pulse Width Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the
asserted IOR signal.
16-Bit Master Drive IDE IOR Command Recovery Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOR
must be deasserted between transfers.
Function
16-Bit Master Drive IDE IOW Command Pulse Width Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the
asserted IOW signal.
16-Bit Master Drive IDE IOW Command Recovery Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOW
must be deasserted between transfers.
Function
16-Bit Slave Drive IDE IOR Command Pulse Width Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the
asserted IOR signal.
16-Bit Slave Drive IDE IOR Command Recovery Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOR
must be deasserted between transfers.
Function
16-Bit Slave Drive IDE IOW Command Pulse Width Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the
asserted IOW signal.
16-Bit Slave Drive IDE IOW Command Recovery Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOW
must be deasserted between transfers.
PRELIMINARY
131
Index=48H with a 32-bit access
Index=4EH with an 8-bit access
Index=4FH with an 8-bit access
Index=4CH with an 8-bit access
Index=4DH with an 8-bit access
CY82C693UB
Default
000000H
0011
0011
Default
0011
0011
Default
0110
1110
Default
0011
0011
Default
0110
1110