CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 96
CY82C693UB
Manufacturer Part Number
CY82C693UB
Description
Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
1.CY82C693UB.pdf
(164 pages)
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OCW1: INTC2 Interrupt Operational Command Word 1 (Read/Write) - I/O Address=0A1H
All Mask Bits are cleared by writing ICW1.
OCW2: INTC2 Interrupt Operational Command Word 2 (Write Only) - I/O Address=0A0H
Bit
7
6
5
4
3
2
1
0
Bit
7:5
4
3
2:0
Function
IR7 Mask Control:
0:
1:
IR6 Mask Control:
0:
1:
IR5 Mask Control:
0:
1:
IR4 Mask Control:
0:
1:
IR3 Mask Control:
0:
1:
IR2 Mask Control:
0:
1:
IR1 Mask Control:
0:
1:
IR0 Mask Control:
0:
1:
Function
Command Control:
000:
001:
010:
011:
100:
101:
110:
111:
Controller Initialization Control:
0:
1:
Operational Command Word Selection Control:
0:
1:
These three bits select which interrupt channel is controlled by the specific commands.
000:
001:
010:
011:
Not Masked
Masked
Not Masked
Masked
Not Masked
Masked
Not Masked
Masked
Not Masked
Masked
Not Masked
Masked
Not Masked
Masked
Not Masked
Masked
Clear Rotate in Auto EOI
Non-specific EOI Command
No Command
Specific EOI Command
Set Rotate on AEOI
Rotate on non-specific EOI
Specific Rotate Command
Rotate on specific EOI
This is an Operational Command Word Write
This is an Initialization Command Word Write (and begins the Initialization
Sequence.)
This is a write to OCW2
This is a write to OCW3
Channel 0 (IRQ8)
Channel 1 (IRQ9)
Channel 2 (IRQ10)
Channel 3 (IRQ11)
PRELIMINARY
100:
101:
110:
111:
Channel 4 (IRQ12)
Channel 5 (IRQ13)
Channel 6 (IRQ14)
Channel 7 (IRQ15)
96
CY82C693UB
Default
0
0
0
0
0
0
0
0
Default
000
0
0
000
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