CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 21

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

on terminal count, Hardware retriggerable one-shot, Rate gen-
erator, Square wave generator, Software triggered strobe, and
Hardware retriggerable strobe. The output of Counter 0 is in-
ternal only (can be programmed to generate interrupts). The
output of Counter 1 is also internal and works with the AT re-
fresh logic to generate ISA refresh cycles. The output of
Counter 2 comes out on the SPKR pin and can be used in any
of the modes for a variety of functions, including generating a
square wave to an external speaker.
DMA Controllers
The CY82C693UB contains two 8237-compatible DMA con-
trollers cascaded together to provide seven separate DMA
channels. Internally, each controller is a 4-channel DMA de-
vice which generates the memory address and control signals
necessary to transfer data between an ISA peripheral device
and system memory (via the PCI bus). The two DMA control-
lers (DMACs) are configured to provide four 8-bit DMA chan-
nels and three 16-bit DMA channels. Channel 0 of the 16-bit
DMAC is used to cascade the two controllers. The DMA con-
trollers support type A, B, and F transfer rates.
The DMACs operate in one of three states at all times: IDLE,
PROGRAM, or ACTIVE.
After the DMACs have been initialized, they remain in IDLE
until a DMA request signal is asserted. Once a DMA request
is seen, the DMAC that receives the request will enter the AC-
TIVE state, or if the system is programming the internal con-
figuration registers of a DMAC, it will enter the PROGRAM
state. In the IDLE state, the DMACs do nothing aside from
sampling the DMA request signals and configuration register
decode signals. If a request comes in at the same time as a
configuration register access, the register access is executed
first.
The first thing the DMACs do, after entering the ACTIVE state,
is arbitrate for the PCI bus. The CY82C693UB must obtain
ownership of the PCI bus regardless of whether the target is
on PCI or not. After the PCI bus has been won, the
CY82C693UB will issue DMA acknowledge to the highest pri-
ority requestor. The DMA transfer is then free to begin. The
DMAC is in control of the ISA command signals and IOCHRDY
during DMA.
The DMACs will enter the PROGRAM state any time a PCI
address is decoded to I/O Port 22H. This is the Index Register
Port (IRP) for DMAC configuration space. A read or write to
Port 23H should immediately follow the write to the IRP. Port
23H is the Data Register Port (DRP).
DMA Controller Transfer Modes
The DMACs can be programmed (on a per channel basis) to
transfer data in four modes: Single Transfer Mode, Block
Transfer Mode, Demand Transfer Mode, or Cascade Mode.
In Single Transfer Mode, the DMACs will transfer one
byte/half-word of data (8 or 16 bits) at a time. A DMAC must
arbitrate for the PCI bus after each transfer. This ensures that
the PCI bus bandwidth will not be completely consumed by an
ISA peripheral. The Word Count Register (WCR) will decre-
ment from the block count until zero is reached. If autoinitializ-
ing is selected, the channel will reinitialize itself for the next
DMA transfer. Otherwise, the channel will be masked until it is
initialized.
In Block Transfer Mode, the DMACs will hold onto ownership
of the PCI bus and continue performing transfers until the
PRELIMINARY
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WCR is decremented to zero. This will give the best DMA per-
formance but runs the risk of degrading overall system perfor-
mance by tying up the PCI bus for long periods. The channel
must once again be initialized/autoinitialized after the block
transfer has been completed.
In Demand Transfer Mode, the DMACs will continue perform-
ing transfers until the WCR contains zero or the DMA request
is negated. The peripheral will negate its DMA request when
it is not ready to transfer data (e.g., an I/O device with its buffer
full). When the device is ready to resume the transfer, it must
assert its DMA request again and rearbitrate for the ISA and
PCI buses. This allows higher priority bus masters to access
the buses while the peripheral involved in the DMA cycle is not
ready. However, if the device remains ready to transfer data, it
can hold its DMA request active and perform back-to-back
transfers without arbitrating between transfers. The channel
must be initialized/autoinitialized after the block transfer has
been completed.
Seven DMA channels are available in the CY82C693UB. If
additional channels are required, channels may be placed in
Cascade Mode. When a channel is in Cascade Mode, external
8237 HOLDREQ and HLDA signals can be routed to the chan-
nel’s DMA request and DMA acknowledge signals respective-
ly. The arbitration rotating protocol will be maintained.
Read, Write, and Verify transfers can be performed in any of
the transfer modes. Any channel may also be configured to
perform autoinitialization. During autoinitialization, the original
values are automatically restored to the Base Address Regis-
ter and Word Count Register from the Current Address Regis-
ter and Current Word Count Register when the block transfer
is complete (zero in the WCR or an EOP is signalled from the
peripheral). The channel will not automatically be masked if
autoinitialization is selected.
IDE Controller
The CY82C693UB contains an integrated, dual-channel PCI
to IDE bridge. The IDE controller conforms to ANSI modes 0,
1, 2, 3, and 4 for PIO (Programmed I/O) transfers. Single-word
and multi-word DMA transfer modes 0, 1, and 2 are also sup-
ported. ATAPI (CD ROM) protocols are allowed with pre-fetch-
ing disabled. The controller allows for CHS (Cylin-
der-Head-Sector) or LBA (Logical Block Address) addressing.
Each of the two channels support two devices for a maximum
of four IDE devices in the system. The controller allows for PIO
pre-fetching, post writing, and DMA PCI mastering in order to
increase overall system performance.
Real-Time-Clock
The CY82C693UB contains 14 bytes for a complete
time-of-day clock with alarm, one hundred year calendar, a
programmable periodic interrupt generator, and 242 bytes of
battery-backed “scratch” RAM. The entire Real-Time-Clock
(RTC) remains operational under normal or battery power. A
32 kHz oscillator is integrated as part of the RTC. Only an
external crystal and a battery are required to complete the
clock circuit.
RTC Address Map
The internal RTC contains 256 bytes of battery-backed RAM
(14 bytes for clock data and 242 bytes of user-definable RAM).
Figure 2 shows the address map.
CY82C693UB