CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 134

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

Register 3: Status Registers (Read/Write) - Index=06H with a 16-bit access
Register 4: Revision ID Number (Read Only) - Index=08H with an 8-bit access
Bit
15
14
13
12
11
10:9
8
7
6:0
Bit
7:0
Function
Detected Parity Error:
READ:
0:
1:
WRITE:
0:
1:
This bit is set to 1 whenever the USB Host Controller detects a parity error, even if the Parity
Error Detection Enable bit (command register, bit 6) is disabled.
PCI SERR Status:
READ:
0:
1:
WRITE:
0:
1:
This bit is set to 1 when the USB Host Controller detects a PCI address parity error.
PCI Master-Abort
READ:
0:
1:
WRITE:
0:
1:
CY82C693UB Detection of Target-Abort (from another PCI target)
READ:
0:
1:
WRITE:
0:
1:
CY82C693UB Assertion of Target-Abort (CY82C693UB is the target)
READ:
0:
1:
WRITE:
0:
1:
DEVSEL Timing Status:
These register bits are Read Only and will always read as 01 (medium timing)
Data Parity Reported. Not supported by CY82C693UB (PERR)
Fast Back-to-Back Transfer Capable. This Read Only bit will always return 1
Reserved. Always 0.
Function
Current Revision of the Part (00000000)
No PCI Master-Abort occurred
PCI Master-Abort occurred
No change to register
Clear register
No PCI Target-Abort occurred
PCI Target-Abort occurred
No change to register
Clear register
No PCI Target-Abort occurred
PCI Target-Abort occurred
No change to register
Clear register
No Parity Error Detected
Parity Error Detected
No change to register
Clear register
No Parity Error Detected
Parity Error Detected
No change to register
Clear register
PRELIMINARY
134
CY82C693UB
Default
0
0
0
0
0
01
0
1
0
Default
00H