CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 90

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

CY82C693UB Interrupt Controller Registers
There are two Interrupt controllers cascaded together inside
the CY82C693UB. (INTC1 and INTC2). The controllers each
accept up to eight requests (from the Interrupt Request pins),
resolve interrupt priority, assert the INTR pin to the CPU, and,
in response to an interrupt acknowledge cycle, will return the
appropriate Interrupt Vector (an address that points to the in-
terrupt service routine).
A subset of the interrupt request lines are dedicated for spe-
cific system operations. They include: IRQ0 - The output of the
system timer inside the CY82C693UB; IRQ1 - The keyboard
request interrupt; IRQ2 - The cascade between INTC1 and
INTC2; IRQ8 - The alarm from the Real-Time-Clock; IRQ12 -
The mouse request interrupt; and IRQ13 - The coproccessor
error signal. These interrupt requests are not generally avail-
able for other interrupt functions. IRQ0 and IRQ2 are not
brought out to external CY82C693UB pins (the connection is
made internally). The rest of the dedicated interrupts are avail-
able when CY82C693UB functions are disabled. IRQ1 is avail-
able on the KBCLK (keyboard clock) pin when the internal key-
board controller is disabled. IRQ8 is available on the PSRSTB
(power supply to battery source signal for the RTC) when the
internal RTC is disabled. IRQ12 is available on the MSCLK
(mouse clock) pin when the internal keyboard controller is dis-
abled. IRQ13 is available on the FERR pin
IRQ[15:14], IRQ[11:9], and IRQ[7:3] are available for system
use. There are traditional functions for these interrupt re-
quests. However, the system designer can configure these in-
puts for many uses. The traditional uses are as follows: IRQ3
- Serial Port 2 interrupt request; IRQ4 - Serial Port 1 interrupt
request; IRQ5 - Parallel Port 2 interrupt request; IRQ6 - Floppy
Disk Controller interrupt request; IRQ7 - Parallel Port 1 inter-
rupt request; IRQ9 - ISA/PCI slot interrupt request; IRQ10 -
ISA/PCI slot interrupt request; IRQ11 - ISA/PCI slot interrupt
request; IRQ14 - Hard Disk interrupt request; and IRQ15 -
ISA/PCI slot interrupt request.
When any number of interrupt requests are asserted to the
CY82C693UB, bits are set in the Interrupt Request Register
(IRR) corresponding to the asserted interrupt requests. The In
Service Register (ISR) will store bits corresponding to all inter-
rupt channels that are currently being serviced. The Interrupt
Mask Register (IMR) will allow interrupt requests to be gated
(masked off) by setting bits corresponding to the channels to
be masked. All of the above registers output to priority resolu-
tion logic. The resolution logic will evaluate the inputs, deter-
mine a priority for interrupt servicing, assert INTR to the CPU,
and latch the highest priority (non-masked) channel value into
the ISR. A vector corresponding to the highest priority
(non-masked) interrupt will be provided to the PCI bus in re-
sponse to an Interrupt Acknowledge cycle.
The sequence for handling a peripheral interrupt is as follows:
1. Interrupt requests (one or multiple) are issued to the
2. Using the values stored in the IRR, ISR, and IMR, the next
CY82C693UB through the IRQ pins, the PCIINT pins, or the
internal requestors. This sets the corresponding bit(s) in the
IRR.
interrupt to be serviced is determined. INTR is asserted to
the CPU.
PRELIMINARY
90
The ISR will be reset on an End-of-Interrupt (EOI). An EOI is
a special command that the interrupt handler code must issue
to the CY82C693UB. A specific EOI can be sent to the
CY82C693UB to clear a specific bit in the ISR, or the highest
priority interrupt can be cleared (non-specific). Masked inter-
rupts will not be cleared for a non-specific EOI. If Automatic
End-of-Interrupt (AEOI) is programmed, the highest priority
(non-masked) interrupt bit will be cleared in the ISR after the
Interrupt Acknowledge cycle
The priority can be programmed to be fixed, a specific rotation,
or automatic rotation. In fixed priority mode, Interrupt Request
0 (IR0) is the highest priority followed in descending order by
IR1, IR8, IR9, IR10, IR11, IR12, IR13, IR14, IR15, IR3, IR4,
IR5, IR6, and IR7 (the lowest priority). This priority scheme
comes from the fact that INTC2 is cascaded through IR2 of
INTC1. Fixed priority is the default. Rotation or interrupt polling
must be programmed. If an interrupt has its bit set in the ISR,
all lower priority interrupts will not cause the assertion of INTR
to the CPU (until the ISR bit is cleared). Specific Rotation al-
lows the highest priority to be changed. All Interrupt Requests
wrap-around in priority (e.g., if IR3 is selected to highest prior-
ity, the priority changes to IR3–IR7 followed by IR0-IR2 for
each controller in descending order.). If Automatic Rotation is
programmed, the last Interrupt Request to be serviced is given
lowest priority. Polling mode will inhibit the CY82C693UB from
generating INTR to the CPU. The CPU must poll (read the IRR
register) to determine which interrupt to take.
The Interrupt Controllers are programmed using Initialization
Command Words (ICWs) and Operational Command Words
(OCWs).
To initialize each controller, a sequence of four bytes must be
sent to the corresponding controller. An I/O write to address
020H (for INTC1) and 0A0H (for INTC2) with 1 on bit 4 of the
data bus will begin the initialization sequence. The interrupt
controller will automatically reset the Initialization Word Count
Register, latch ICW1 into the controller, select Fixed Priority,
assign IR7 the highest priority, clear the Interrupt Mask Regis-
ter, set the Slave mode address to 7 (for cascading), disable
Special Mask Mode, and select the IRR for Status Read oper-
ations (the contents of the IRR will be returned on a Status
Read). The next three I/O writes to address 021H (for INTC1)
and 0A1H (for INTC2) will load ICW2 through ICW4 for each
controller. Executing an I/O write to 020H (for INTC1) and
0A0H (for INTC2) will cause the ICW writing to terminate and
will begin writing OCW2 or OCW3.
The OCWs allow the controllers to be reconfigured during nor-
mal operation. OCW1 is located at I/O address 021H (for
INTC1) and 0A1H (for INTC2) whenever the controller is not
being initialized. OCW2 and OCW3 are at I/O location 020H
(for INTC1) and 0A0H (for INTC2) with data bit 4 set to zero.
Data bit 3 controls whether OCW2 (bit3=0) or OCW3 (bit3=1)
is being written.
-
3. When the CPU recognizes the assertion of INTR, it re-
4. When the CY82C693UB sees a PCI Interrupt Acknowledge
5. The CPU uses the vector to jump to the Interrupt Service
sponds with an Interrupt Acknowledge Cycle. The Interrupt
Acknowledge Cycle is passed on to the PCI bus.
Cycle, it will respond with a vector (address corresponding
to the appropriate Interrupt Service Routine).
Routine and begins execution of the interrupt handler
CY82C693UB