CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 146

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

Register 20: HcRhPortStatus[1:2] (Read/Write) - Index=54H, 58H with a 32-bit access (continued)
Note: This register is reset by the USBReset state.
Register 21: HceControl (Read/Write) - Index=100H with a 32-bit access
Note: This register is used to enable and control the legacy keyboard and mouse emulation hardware and report various
status information.
Bit
2
1
0
Bit
31:9
8
7
6
5
4
3
2
1
0
Function
READ:
Port Suspend Status.
0:
1:
WRITE:
Set Port Suspend. Writing a ‘1’ sets PortSuspendStatus. Writing a ‘0’ has no effect
READ:
Port Enable Status.
0:
1:
WRITE:
Set Port Enable. Writing a ‘1’ sets PortEnableStatus. Writing a ‘0’ has no effect.
READ:
Current Connect Status.
0:
1
Note: If DeviceRemovable is set (not removable) this bit is always ‘1’.
WRITE:
Clear Port Enable. Writing a ‘1’ clears PortEnableStatus. Writing a ‘0’ has no effect.
Function
Reserved.
A20 State:
Indicates current state of Gate A20 on keyboard controller. Used to compare against value
written to 60H when GateA20Sequence is active.
IRQ12 Active:
Indicates that a positive transition on IRQ12 from keyboard controller has occurred. Software
may write a ‘1’ to this bit to clear it (set it to ‘0’). Software write of a ‘0’ to this bit has no effect.
IRQ1 Active:
Indicates that a positive transition on IRQ1 from keyboard controller has occurred. Software
may write a ‘1’ to this bit to clear it (set it to ‘0’). Software write of a ‘0’ to this bit has no effect.
Gate A20 Sequence:
Set by the Host Controller when a data value of D1H is written to I/O port 64H. Cleared by
the Host Controller on write to I/O port 64H of any value other than D1H.
External IRQEn:
When set to ‘1’, IRQ1 and IRQ12 from the keyboard controller will cause an emulation inter-
rupt. The function controlled by this bit is independent of the setting of the EmulationEnable
bit in this register.
IRQEn:
When set the Host Controller will generate IRQ1 or IRQ12 as long as the OutputFull bit in
HceStatus is set to ‘1’. If the AuxOutputFull bit of HceStatus is ‘0’ then IRQ1 is generated and
if it is ‘1’, then an IRQ12 is generated.
Character Pending:
When set, an emulation interrupt will be generated when the OutputFull bit of the HceStatus
register is set to ‘0’.
Emulation Interrupt:
This bit is a static decode of the emulation interrupt condition.
Emulation Enable:
When set to ‘1’ the Host Controller will be enabled for legacy emulation. The Host Controller
will decode accesses to I/O registers 60H and 64H and generate IRQ1 and/or IRQ12 when
appropriate. Additionally, the Host Controller will generate an emulation interrupt at appropri-
ate times to invoke the emulation software.
Port is not suspended
Port is selectively suspended
Port disabled
Port enabled
No device connected
Device connected
PRELIMINARY
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CY82C693UB
Default
0
0
0
Default
0H
0
0
0
0
0
0
0
0
0