CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 29

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CY82C693UB

Manufacturer Part Number
CY82C693UB
Description
Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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ISA Interface Signals (continued)
Name
IRQ1/KBCLK
IRQ[15:14],
IRQ[11:9]
IRQ[7:3]
IRQ12/MSCLK
IRQ8/PSRSTB
INTR/KBATMODE
NMI
ATCLK
ALE
DRQ7/GPIO8/
SMIACT
DRQ6/GPIO7/
OVRCUR
DRQ5/GPIO6/
PWREN
I/O
I/O
I
I/O
I
I/O
O
O
I/O
I/O
I/O
I/O
PRELIMINARY
Description
Keyboard Clock/Interrupt Request 1: This signal is the keyboard clock connected to
the keyboard connector if the internal keyboard controller is used. Otherwise, it pro-
vides IRQ1 (the keyboard controller interrupt input) if an external keyboard controller
is desired.
Interrupt Request Inputs: These signals provide interrupt requests for CPU
interrupters.
Mouse Clock/Interrupt Request 12: This signal is the mouse clock connected to the
mouse connector if the internal keyboard controller is used. Otherwise, it provides
IRQ12 (the mouse controller interrupt input) if an external keyboard controller is
desired.
Power Strobe/Interrupt Request 8: If the internal Real-Time-Clock (RTC) is used, this
is the power strobe input. If an external RTC is desired, this is interrupt request 8
(traditionally the RTC interrupt).
CPU Interrupt/Keyboard AT Mode: This is the INTR (interrupt request) signal that is
connected directly to the CPU’s INTR pin. When interrupt requests come in to the
CY82C693UB, it will assert INTR to the CPU. On power-up this signal should be
pulled-down through a 1K Ohm resistor to ground if PS/2 keyboard support is desired.
Non-maskable CPU Interrupt: This is the NMI (non-maskable interrupt request) signal
that is connected directly to the CPU’s NMI pin. When the CY82C693UB detects a fatal
error (such as a PCI parity error), it will assert NMI to the CPU.
AT Clock: This signal can be used to provide the system ISA (AT) bus clock. It can be
internally programmed to generate different ISA frequencies.
Bus Address Latch Enable: This signal is the ISA BALE signal used by peripherals to
latch the cycle address, AEN, and SBHE.
ISA DMA/Master Request Input 7/General Purpose I/O 8/USB Host Controller SMIACT
Input: This signal is used by external ISA peripherals to request mastership of the ISA
bus for DMA or ISA MASTER cycles. They can be programmed to be GPIO if the DREQ
signals are connected to an external (’157 type) TTL device to time multiplex (using
the ATCLK as the selector signal) the DMA requests onto DRQ[3:0]. When USB Host
Controller is enabled, this signal becomes SMI Active input, which is used to mask the
SMI output while in SMM. Pull-up is required for SMIACT if unused.
ISA DMA/Master Request Input 6/General Purpose I/O 7/USB Host Controller OVR-
CUR input: This signal is used by external ISA peripherals to request mastership of
the ISA bus for DMA or ISA MASTER cycles. They can be programmed to be GPIO if
the DREQ signals are connected to an external (’157 type) TTL device to time multiplex
(using the ATCLK as the selector signal) the DMA requests onto DRQ[3:0]. When USB
Host Controller is enabled, this signal becomes Over-current Detection input.
OVRCUR is asserted when downstream ports exceed their current allocation. This
input causes power to be disabled and is reported through the hub and port status
register. Pull-up required for OVRCUR if unused.
ISA DMA/Master Request Input 5/General Purpose I/O 6/USB Host Controller PWREN
output: This signal is used by external ISA peripherals to request mastership of the
ISA bus for DMA or ISA MASTER cycles. They can be programmed to be GPIO if the
DREQ signals are connected to an external (’157 type) TTL device to time multiplex
(using the ATCLK as the selector signal) the DMA requests onto DRQ[3:0]. When USB
Host Controller is enabled, this signal becomes Port Power Enable output. The global
power to USB ports is controlled by this signal. If NoPowerSwitching in HcRhDescrip-
torA (USB Host Controller Operational Register) is set, this signal is always active.
29
CY82C693UB

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