CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 27

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

PCI Interface Signals (continued)
ISA Interface Signals
Name
REQ[1]/SGNT
REQ[0]/PGNT
GNT[3]/DISARB
GNT[2]/SQWV
GNT[1]/SREQ
GNT[0]/PREQ
Name
SA[19:4]/
IDE[15:0]
SA[3:0]
SD[15:0]
XD7/IDEIRQ0
GPIO0
I/O
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
I/O
PRELIMINARY
Description
PCI Bus Request 1/ Secondary PCI Grant: If the internal PCI arbiter is enabled, this
signal is connected to the individual bus request from PCI peripheral number 1. When
a combination of the bus requests is asserted, the CY82C693UB will resolve the pri-
ority and give the grant to the highest priority master.
If the internal PCI arbiter is disabled (by strapping pin 194 LOW through a 1K Ohm
resistor), this signal becomes a RESERVED input. In the CY82C693UBU this signal
will optionally become the secondary grant input to grant the PCI bus to the USB Host
Controller.
PCI Bus Request 0/ Primary PCI Grant: If the internal PCI arbiter is enabled, this signal
is connected to the individual bus request from PCI peripheral number 0. When a
combination of the bus requests is asserted, the CY82C693UB will resolve the priority
and give the grant to the highest priority master.
If the internal PCI arbiter is disabled (by strapping pin 194 LOW through a 1K Ohm
resistor), this signal becomes the PGNT input. PGNT is driven active by the external
PCI arbiter to grant ownership of the PCI bus to the CY82C693UB.
PCI Bus Grant 3/ PCI Arbiter Disable: This signal is connected to bus grant of PCI
peripheral #3. When a combination of the bus requests is asserted, the CY82C693UB
will resolve the priority and assert grant to the highest priority master. During power-up,
this signal acts as a strapping option to disable the PCI arbiter within the CY82C693UB.
An external PCI arbiter must be provided. When the internal arbiter is disabled, several
other signals change function to provide the request/grant signals from the
CY82C693UB to the external arbiter.
PCI Bus Grant 2/ RTC Square Wave Output: This signal is connected to bus grant of
PCI peripheral #3. When a combination of the bus requests is asserted, the
CY82C693UB will resolve the priority and assert grant to the highest priority master.
If the internal PCI arbiter is disabled (pin 194 strapped LOW during power up), this pin
drives the output of the square wave generator in the Real-Time-Clock.
PCI Bus Grant 1/ Secondary PCI Request: If the internal PCI arbiter is enabled, this
signal is connected to the individual bus grant to PCI peripheral number 1. When a
combination of the PCI bus requests is asserted, the CY82C693UB will resolve the
priority and assert grant to the highest priority master.
If the internal PCI arbiter is disabled (by strapping pin 194 LOW through a 1K Ohm
resistor), this signal becomes a RESERVED output. In the CY82C693UBU this signal
will optionally become the secondary request output to request ownership of the PCI
bus for the USB Host Controller.
PCI Bus Grant 0/ Primary PCI Request: If the internal PCI arbiter is enabled, this signal
is connected to the individual bus grant to PCI peripheral number 0. When a combina-
tion of the bus requests is asserted, the CY82C693UB will resolve the priority and
assert grant to the highest priority master.
If the internal PCI arbiter is disabled (by strapping pin 194 LOW through a 1K Ohm
resistor), this signal becomes the PREQ output. PREQ is driven active by the
CY82C693UB to request ownership of the PCI bus for ISA or IDE DMA and USB Host
Controller (if no separate arbitration used) cycles.
Description
ISA Address Bus/PCI IDE Data Bus: These signals provide most of the address for the
ISA bus as well as the data path for IDE.
ISA Address: These signals provide the rest of the ISA address.
System Data Bus: These signals connect directly to the ISA data bus.
XD Bus, Bit 7/Programmable Interrupt Request 0/General Purpose I/O 0: If zero TTL
is desired for XD bus support (BIOS ROM data, external keyboard controller data, and
external RTC data), this is bit 7 of the data bus. Otherwise, this is user-selectable to
provide support for a Programmable Interrupt Request or a general purpose I/O. As a
GPIO, this signal can either reflect the contents of an internal register bit (output) or
set an internal register bit to the value driven on the line (input).
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CY82C693UB