CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 24

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

External Reset Control
System reset is normally controlled by the CY82C693UB.
When the PWGD signal is deasserted, the CY82C693UB’s
internal circuitry is reset and CPURST is driven active. PCIR-
ST is placed in high-impedance until the CY82C693UB sam-
ples pin 172 HIGH (default with internal pull-up). Then PCIRST
is driven active. When PWGD goes active, the CY82C693UB
will continue to drive CPURST and PCIRST active for a mini-
mum of 1 ms.
If an external reset agent is desired, pin 172 should be pulled
to ground through a 1K Ohm resistor. If pin 172 is sampled
LOW while PWGD is deasserted, the PCIRST output buffer
will be placed in high-impedance. This requires the external
agent to drive PCIRST (internal pull-up resistor is used). Once
PWGD is asserted, the state of pin 172 will be internally
latched into the CY82C693UB. If pin 172 is pulled LOW,
PCIRST becomes an input to the CY82C693UB. CPURST will
still be driven active for a minimum of 1ms after the assertion
of PWGD. After PWGD goes active, the PCIRST input can be
driven active by an external agent to reset the internal circuitry
of the CY82C693UB. PCIRST will also be inverted and driven
out on the CPURST output. ISA bus is also reset by the asser-
tion of PCIRST. PCIRST is a synchronous input (sampled on
PCI clock). The minimum active PCIRST must be 80 PCI clock
cycles. This insures that AT components inside the
CY82C693UB (such as the keyboard controller) are properly
reset.
FREQACK Bypassing
NOTE: Flush Request/Acknowledge signaling must be by-
passed if an acknowledge is not sent to the CY82C693UB.
Otherwise DMA will not work.
The CY82C693UB uses a flush request/acknowledge hand-
shake. The flush request/acknowledge insures that there is a
coherent path whenever ISA or IDE DMA masters attempt to
access system memory. Data coherency may be violated any-
time there is a temporary storage element (such as a post write
buffer) that does not monitor transfers of data to provide the
most up-to-date copy. In other words, data may be stored in a
post-write buffer which is more current than the data in DRAM
memory. An ISA/IDE DMA master may get the wrong data if
the access is allowed to proceed to main memory “around the
post-write buffer.”
To eliminate a data coherency problem, the CY82C693UB will
issue a “flush request” before allowing an ISA/IDE DMA trans-
fer to proceed. Flush request is signalled when the
CY82C693UB asserts FREQACK for one PCI clock cycle. The
CY82693UB will then deassert FREQACK, place the output in
high-impedance, and begin monitoring the input. When all
post-write buffers have been emptied, the system controller
will assert FREQACK for one PCI clock cycle. This signifies an
acknowledge. The CY82C693UB will proceed with the DMA
transfer.
If a coherent path to memory can be guaranteed without flush-
ing storage elements (i.e., the post-write buffers “snoop” trans-
actions and provide current data, or there are no post-write
buffers), the flush request/acknowledge protocol may be by-
passed. If PCI configuration register 4DH, bit 6 is set to “1”, the
flush request will be internally acknowledged. The FREQACK
signal (pin 190) will be unused and placed in a high-impedance
state.
PRELIMINARY
24
When the flush request/acknowledge protocol is bypassed,
the RTC interrupt request (IRQ8) may be optionally driven on
pin 190. This can be used to provide immediate, non-masked
servicing for Real-Time-Clock interrupts. External IRQ8 gen-
eration is controlled by PCI configuration register 4DH, bit 5. If
bit 5 is “0”, IRQ8 from the RTC circuit is only routed internally
to the integrated interrupt controller. It is not available on an
external CY82C693UB pin. If, however, register 4DH, bit 5 is
set to “1”, the IRQ8 output from the RTC circuitry is masked to
the internal interrupt controller, and IRQ8 is driven on pin 190
of the CY82C693UB. NOTE: If the flush request/acknowledge
protocol is not bypassed, FREQACK is driven on pin 190 and
if register 4DH, bit 5 is set to “1” the RTC interrupt will only be
masked (IRQ8 will not be available externally).
32-Bit I/O Space Decode
As X86 processors only support 64 Kbytes of I/O space, the
CY82C693UB’s IDE controllers only decode the lower 16 bits
of the PCI address. This is sufficient for PC chipset applica-
tions. However, for stand-alone operation, it may become nec-
essary to decode 32 address bits (4GB) of I/O space. If PCI
configuration register 4DH, bit 4 is set to “1”, 32-bits are de-
coded for I/O space. This effects the format of IDE Base Ad-
dress Registers in PCI configuration space. When register
4DH, bit 4 is “0”, the upper 16-bits of the IDE Base Address
Registers (10H, 14H, and 20H) are hardwired to 0000H. When
register 4DH, bit 4 is “1”, the upper 16-bits are readable and
writable. The value written corresponds to the decoded ad-
dress range (as specified in the PCI specification, revision
2.1).
1 Mbyte ROM Decode
The CY82C693UB can support Extended ROM decoding up
to 1 MB at the top of memory space. If bit 3 of the PCI config-
uration register 4DH is set to “0”, 512 KB Extended ROM ad-
dress decoding is supported (FFF80000H to FFFFFFFFH). If
bit 3 is set to “1” 1 MB Extended ROM address decoding is
enabled (FFF00000H to FFFFFFFFH).
Universal Serial Bus (USB) Host Controller
The CY82C693UB contains a USB host controller. The Host
Controller integrates a root hub with two USB ports; therefore,
two USB peripheral devices can be connected to the
Hardware
Software
Figure 4. USB System Domains
Device
USB
Host Controller
Host Controller
HCI
USB Driver
Driver
Device
USB
CY82C693UB
USB
Scope of
OpenHCI