MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 133

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MC68HC708XL36

Manufacturer Part Number
MC68HC708XL36
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
DMA Control
Register 1
23-dma_b
MOTOROLA
Address: $004C
DMA control register 1:
BB1 and BB0 — Bus Bandwidth Control Bits
Reset:
Read:
Write:
These read/write bits control the ratio of DMA/CPU bus activity during
a DMA transfer. As
or 100% of the bus bandwidth. Reset clears bits BB1 and BB0.
Figure
transfers with DMA bus bandwidths of 25%, 50%, and 67%.
Freescale Semiconductor, Inc.
BB1:BB0
For More Information On This Product,
Enables channels to transfer data when DMA service requests
occur.
Enables channels to generate CPU interrupt requests.
Controls how much of the bus bandwidth the DMA uses.
00
01
10
11
Bit 7
BB1
0
15,
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Figure 14. DMA Control Register 1 (DC1)
Table 6. DMA/CPU Bus Control Selection
Figure
BB0
6
0
16, and
DMA
Table 6
DMA Bus Cycles
TEC2
5
0
All (100%)
2 (25%)
2 (50%)
2 (67%)
shows, the DMA can use 25%, 50%, 67%,
Figure 17
IEC2
4
0
DMA Transfer
show the timing of DMA
TEC1
3
0
IEC1
2
0
CPU Bus Cycles
6 (75%)
2 (50%)
1 (33%)
0 (0%)
MC68HC708XL36
TEC0
DMA Registers
1
0
IEC0
Bit 0
0
DMA
133

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