MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 269

• Manufacturer Part Number: MC68HC708XL36
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

35-sci_d
MOTOROLA
NOTE:
NOTE:
NOTE:
When SCI receiver DMA service requests are enabled (DMARE = 1),
then SCI receiver CPU interrupt requests are disabled, and the state of
the ILIE bit has no effect.
TE — Transmitter Enable Bit
Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RE — Receiver Enable Bit
Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RWU — Receiver Wakeup Bit
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
TxD pin. If software clears the TE bit, the transmitter completes any
transmission in progress before the TxD returns to the idle condition
(logic 1). Clearing and then setting TE during a transmission queues
an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver but does not affect receiver interrupt flag bits.
Reset clears the RE bit.
This read/write bit puts the receiver in a standby state during which
receiver interrupts are disabled. The WAKE bit in SCC1 determines
whether an idle input or an address mark brings the receiver out of the
standby state and clears the RWU bit. Reset clears the RWU bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Transmitter enabled
0 = Transmitter disabled
1 = Receiver enabled
0 = Receiver disabled
1 = Standby state
0 = Normal operation
Go to: www.freescale.com
SCI
MC68HC708XL36
I/O Registers
SCI
269