MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 162

• Manufacturer Part Number: MC68HC708XL36
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

MON
Data Format
Break Signal
Baud Rate
MC68HC708XL36
162
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. Transmit and receive baud rates must
be identical.
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When
the monitor receives a break signal, it drives the PA0 pin high for the
duration of two bits and then echos back the break signal.
The bus clock frequency of the MCU in monitor mode is determined by:
The internal monitor firmware performs a division by 256 (for sampling
data); therefore, the bus frequency divided by 256 is the baud rate of the
monitor mode data transfer.
For example, with a 4.9152-MHz external clock and the PC3 pin at logic
1 during reset, data is transferred between the monitor and host at 4800
baud. If the PC3 pin is at logic 0 during reset, the monitor baud rate is
9600.
BIT TIME
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•
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Freescale Semiconductor, Inc.
PA0
For More Information On This Product,
The external clock frequency
The value on the PC3 pin
Whether the phase-locked loop (PLL) is engaged
START
BIT
START
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BIT 0
0
1
BIT 1
2
Figure 2. Monitor Data Format
Figure 3. Break Transaction
3
MON
NO STOP BIT
BIT 2
4
5
BIT 3
6
7
BIT 4
BIT 5
2-BIT DELAY TIME BEFORE 0 ECHO
BIT 6
0
1
BIT 7
2
3
STOP
4
BIT
5
MOTOROLA
6-mon08sp_1p
6
7