MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 181

• Manufacturer Part Number: MC68HC708XL36
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Buffered PWM
Signal Generation
11-tim4_b
MOTOROLA
NOTE:
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to
self-correct in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the TCH0 pin. The TIM channel registers of the linked
pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The TIM channel 0 registers initially
control the pulse width on the TCH0 pin. Writing to the TIM channel 1
registers enables the TIM channel 1 registers to synchronously control
the pulse width at the beginning of the next PWM period. At each
subsequent overflow, the TIM channel registers (0 or 1) that control the
pulse width are the ones written to last. TSC0 controls and monitors the
buffered PWM function, and TIM channel 1 status and control register
(TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1,
is available as a general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered PWM channel whose
output appears on the TCH2 pin. The TIM channel registers of the linked
pair alternately control the pulse width of the output.
Setting the MS2B bit in TIM channel 2 status and control register (TSC2)
links channel 2 and channel 3. The TIM channel 2 registers initially
control the pulse width on the TCH2 pin. Writing to the TIM channel 3
registers enables the TIM channel 3 registers to synchronously control
the pulse width at the beginning of the next PWM period. At each
subsequent overflow, the TIM channel registers (2 or 3) that control the
pulse width are the ones written to last. TSC2 controls and monitors the
buffered PWM function, and TIM channel 3 status and control register
(TSC3) is unused. While the MS2B bit is set, the channel 3 pin, TCH3,
is available as a general-purpose I/O pin.
Freescale Semiconductor, Inc.
For More Information On This Product,
the current PWM period. Writing a larger value in an output
compare interrupt routine (at the end of the current pulse) could
cause two output compares to occur in the same PWM period.
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TIM
Functional Description
MC68HC708XL36
TIM
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