MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 138

• Manufacturer Part Number: MC68HC708XL36
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

DMA
MC68HC708XL36
138
DMAWE — DMA Wait Enable Bit
IFC[2:0] — CPU Interrupt Flag Bits
This read/write bit enables the DMA to operate while in wait mode.
Reset clears the DMAWE bit.
These read/write bits become set when a DMA transfer is complete
or at the end of each transfer loop. IFC2, IFC1, or IFC0 can generate
a CPU interrupt request if the corresponding IECx bit is set in DMA
control register 1. Clear IFC[2:0] by reading them and then writing 0s
to them. Reset clears the IFC[2:0] bits.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = DMA transfer enabled after WAIT instruction
0 = DMA transfer suspended after WAIT instruction
1 = DMA transfer complete
0 = DMA transfer not complete
Go to: www.freescale.com
DMA
MOTOROLA
28-dma_b