MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 146
MC68HC708XL36
Manufacturer Part Number
MC68HC708XL36
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC68HC708XL36.pdf
(376 pages)
- Current page: 146 of 376
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DMA
DMA Block Length
Registers
MC68HC708XL36
146
The read/write block length registers control the number of bytes
transferred. During a block transfer, the DMA compares the number
programmed into the channel’s DMA block length register to the number
in its DMA byte count register. When the byte count reaches the value in
the block length register, the DMA:
If looping is disabled (Lx bit in DMA status and control register = 0), the
DMA then stops the transfer by clearing the TECx bit in DMA control
register 1, disabling the channel. If looping is enabled (Lx bit = 1), the
DMA continues the transfer from the base address.
The block length of a word transfer is twice the number of words. The
state of the DMA block length registers after reset is indeterminate.
•
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
Sets the CPU interrupt flag (IFCx) for that channel in the DMA
status and control register.
Generates a CPU interrupt request if enabled.
Resets the byte count register.
Go to: www.freescale.com
DMA
MOTOROLA
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