MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 195

no-image

MC68HC708XL36

Manufacturer Part Number
MC68HC708XL36
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
25-tim4_b
MOTOROLA
NOTE:
CHxIE — Channel x Interrupt Enable Bit
TIM DMA service requests cannot be used in buffered PWM mode. In
buffered PWM mode, disable TIM DMA service requests by clearing the
DMAxS bit in the TIM DMA select register.
MSxB — Mode Select Bit B
This read/write bit enables TIM CPU interrupts and TIM DMA service
requests on channel x. The DMAxS bit in the TIM DMA select register
selects channel x TIM DMA service requests or TIM CPU interrupt
requests.
Reset clears the CHxIE bit.
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIM channel 0 and TIM channel 2 status and
control registers.
Setting MS0B disables the channel 1 status and control register and
reverts TCH1 to general-purpose I/O.
Setting MS2B disables the channel 3 status and control register and
reverts TCH3 to general-purpose I/O.
Reset clears the MSxB bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Channel x CPU interrupt requests and DMA service requests
0 = Channel x CPU interrupt requests and DMA service requests
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
enabled
disabled
Go to: www.freescale.com
TIM
MC68HC708XL36
I/O Registers
TIM
195

Related parts for MC68HC708XL36