MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 315
MC68HC708XL36
Manufacturer Part Number
MC68HC708XL36
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC68HC708XL36.pdf
(376 pages)
- Current page: 315 of 376
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5-intirq2_a
MOTOROLA
NOTE:
The vector fetch, software clear, or reset and the return of the IRQ1 pin
to logic 1 can occur in any order. A reset clears the CPU interrupt request
and the MODE1 bit, clearing the CPU interrupt request even if the pin
stays low.
If the MODE1 bit is clear, the IRQ1 pin is falling-edge-sensitive only.
With MODE1 clear, a vector fetch or software clear immediately clears
the IRQ1 CPU interrupt request.
The IRQF1 bit in the ISCR register can be used to check for pending
CPU interrupts. The IRQF1 bit is not affected by the IMASK1 bit, which
makes it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ1 pin.
To avoid spurious CPU interrupts caused by noise, mask CPU interrupt
requests in the interrupt routine when using the level-sensitive interrupt
trigger.
•
Freescale Semiconductor, Inc.
For More Information On This Product,
bit latches another CPU interrupt request. If the IRQ1 mask bit,
IMASK1, is clear, the CPU loads the program counter with the
vector address at locations $FFFA and $FFFB.
Return of the IRQ1 pin to logic 1 — As long as the IRQ1 pin is at
logic 0, the IRQ1 CPU interrupt request remains latched.
Go to: www.freescale.com
IRQ
Functional Description
MC68HC708XL36
IRQ
315
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