MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 75

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MC68HC708XL36

Manufacturer Part Number
MC68HC708XL36
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Clock Generator Module (CGM)
Wait Mode
Stop Mode
Break Module (BRK)
Wait Mode
Stop Mode
3-lp24_e
MOTOROLA
The CGM remains active in wait mode. Before entering wait mode,
software can disengage and turn off the PLL by clearing the BCS and
PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from wait mode also can deselect
the PLL output without turning off the PLL.
The STOP instruction disables the CGM and holds low all CGM outputs
(CGMXCLK, CGMOUT, and CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK,
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal clock,
CGMXCLK, divided by two as the source of CGMOUT. When the MCU
recovers from STOP, the crystal clock divided by two drives CGMOUT
and BCS remains clear.
If enabled, the break module is active in wait mode. A DMA-generated
address that matches the break address registers in wait mode sets the
BSW in the break status register.
The DMA can also use the break status and control register as its
destination address in order to write to the BRKA and BRKE bits during
wait mode. A DMA write to the break status and control register sets the
BSW bit.
The break module is inactive in stop mode. The STOP instruction does
not affect break module register states.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Low-Power Modes
Clock Generator Module (CGM)
Low-Power Modes
MC68HC708XL36
75

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